Advanced Micro Devices Corporation

Michael Raab

Karsten Wieczorek

Rolf Stephan

Andy C Wei

Manfred Horstmann

Thorsten E Kammler

Jan Hoentschel

Markus Lenski

Stephan Kruegel

Gert Burbach

Wolfgang Buchholtz

By forming a strained semiconductor layer in a PMOS transistor, a corresponding compressively strained channel region may be achieved, while, on the other hand, a corresponding strain in the NMOS transistor may be relaxed. Due to the reduced junction resistance caused by the reduced band gap of silicon/germanium in the NMOS transistor, an overall performance gain is accomplished, wherein, particularly in partially depleted SOI devices, the deleterious floating body effect is also reduced, due to the increased leakage currents generated by the silicon/germanium layer in the PMOS and NMOS transistor.

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

By direct bonding of two crystalline semiconductor layers of different crystallographic orientation and/or material composition and/or internal strain, bulk-like hybrid substrates may be formed, thereby providing the potential for forming semiconductor devices in accordance with a single transistor architecture on the hybrid substrate.

Technique for forming a substrate having crystalline semiconductor regions of different characteristics located above a crystalline bulk substrate

A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.

Method of forming sidewall spacers

The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Method of filling an opening in a material layer with an insulating material

The present invention is directed to a method of forming metal silicide regions on a gate electrode ( ) and on the source/drain regions ( ) of a semiconductor device ( ). In one illustrative embodiment, the method comprises forming a gate stack ( ) above a semiconducting substrate ( ), the gate stack ( ) being comprised of a gate electrode ( ) and a protective layer ( ), forming a plurality of source/drain regions ( ) in the substrate ( ), and forming a first metal silicide region ( ) above each of the source/drain regions ( ). The method further comprises removing the protective layer ( ) from above the gate electrode ( ) and forming a second metal silicide region ( ) above the gate electrode ( ).

Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device

This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Sidewall spacer based fet alignment technology

This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a gate electrode and sidewall spacer masking procedure both for forming the device isolation features and the source and drain regions. This invention enables an increase of the integration-density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Method for fully self-aligned FET technology

In one embodiment, a protective layer is formed on the top surface of the gate electrode of a transistor device prior to the formation of low resistance metal silicide regions on the drain and source regions. The protective layer prevents the simultaneous formation of a metal silicide region on the gate electrode. Thereafter, a process layer is formed above the source/drain regions and the cover layer that is positioned above the gate electrode. Next, a surface of the process layer is planarized to expose the cover layer, and the cover layer is removed. Then, a metal silicide region is formed above the gate electrode by depositing a layer of refractory metal and performing at least one anneal process.

Method of forming low resistance metal silicide region on a gate electrode of a transistor

The present invention is directed to a semiconductor device (,) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (,) is comprised of a polysilicon gate electrode (,) positioned above a gate insulation layer (,), a plurality of source/drain regions (,) formed in a semiconducting substrate (,), a first metal silicide region (,A) positioned above the gate electrode (,), a second metal silicide region (,) positioned above each of the source/drain regions (,), wherein the first metal silicide region (,A) is approximately 2-10 times thicker than each of the second metal silicide regions (,). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (,) above a layer of polysilicon (,), and converting the refractory metal layer (,) to a metal suicide layer (,), and patterning the metal silicide layer (,) and the gate electrode layer (,) to form a metal silicide region (,A) above the gate electrode (,). The method further comprises forming a plurality of source/drain regions (,) in the substrate (,), forming a second layer comprised of a refractory metal above at least the gate stack (,) and the source/drain regions (,). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (,).

Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same

There is provided a semiconductor device comprising, for example, a MOS structure having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings are formed in a dielectric region of a MOS structure, the thin metal silicide layer on top of a drain/source region is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal is deposited on the metal silicide layer and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.

Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices

A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.

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Radebeul, Germany

Michael Raab