Western Digital Corporation

Adaptec, Inc.

Agere Systems Inc.

Western Digital (singapore) Pte. Ltd.

Michael R Spaur

Robert L Cloke

David Price Turner

Robert Ellis Caddy, Jr

Richard William Hull

Kenneth W Ouyang

Timothy G O'Shaughnessy

Rosser S Wilson

Marc E Acosta

David B Joan

Takashi Asami

Robert P Mento

Marshall D Lee

Francis M Caster, Ii

Min-Hui Wang

In a system having an input signal set with at least two signals having mutually exclusive frequencies f and f being part of the input signal set, whose amplitude is represented in an input digital representation, the amplitudes of each of the at least two signals are digitally represented. A digital representation of the frequency of each of the signals is derived. A digital representation of the sine function and of the cosine function of the frequency of each of the signals is derived based on the digital representation of the frequency. The digital representations of each of the sine and cosine functions is mixed with the input digital representation to derive digital representations of the sine and cosine functions of each of the signals. The digital representations of the sine and cosine functions of each of the signals are processed to derive a digital representation of the amplitude of each of the signals.

Digital processing of pilot-tone amplitudes

The present invention provides a programmable generic read channel control device and circuitry for generating an output signal to control read/write operations. The programmable generic read channel control device includes a set of extension timer, a set of configuration registers, a set of AND gates, and an OR gate. The extension timers are programmed to generate a set of pulses of programmable width in response to a read gate and write gate signal. Each of the pulses is defined by a leading edge pulse and a trailing edge pulse. The set of extension timers includes a short write gate extension timer configured to generate a write gate short leading edge pulse and a write gate short trailing edge pulse defining a write gate short pulse width. The configuration registers store a set of configuration data for the pulses with each configuration register storing one configuration data for either a leading edge or a trailing edge pulse of one of the pulses. The configuration data indicates whether the associated pulse is enabled. The AND gates are arranged to receive the pulses of programmable width with each AND gate receiving either a leading edge or a trailing edge of one of the pulses as a first input. Each AND gate also receiving a configuration data as a second input that allows the first input to be transmitted as an output signal when the configuration data at the second input is enabled. The OR gate is arranged to combine the output signals from the set of AND gates to generate the output signal such that the output signal is generated from only the leading or trailing edges of the pulses from the AND gates receiving the enable signals.

Programmable generic read channel control device

The present invention provides a programmable ADC with bit conversion optimization and method therefor. The programmable ADC includes an amplifier, a programmable clock generator, a comparator, a successive approximation logic, a digital-to-analog converter, and a voltage converter. The amplifier is arranged to sample and hold an input analog signal to be converted into N digital data bits. The programmable clock generator generates a clock signal for each of the N-bits to trigger setting of one of the N-bit digital data bits such that each of the N bits is set during a time optimized for each bit. The comparator is coupled to receive and compare the input analog signal with a successively approximated analog signal to generate a digital output signal. The successive approximation logic is configured to successively set each of the N-bits in response to the digital output signal and the clock signal to generate a successively approximated N-bit digital data. The digital-to-analog converter converts the successively approximated N-bit digital data into a successively approximated analog current signal. The voltage converter has a resistance value for converting the successively approximated analog current signals into the successively approximated analog signal for input to the comparator. The voltage converter is arranged to optimize a time constant defined by the resistance and an output capacitance of the digital-to-analog converter.

Programmable analog-to-digital converter with bit conversion optimization

A system for polling a preamplifier unit to remotely determine pre-established parametric values in a disk drive is disclosed. The disk drive comprises a controller, a preamplifier, and a plurality of transducers. The system for polling the preamplifier comprises means in the controller for generating a succession of serial bit characters each representative of a different pattern. A means is provided for successively transferring said serial bit characters from the controller to the preamplifier unit. A plurality of individual bit lines are provided in the preamplifier unit representative of at least one parametric value. A means is included in the preamplifier unit for comparing each serial bit pattern character received with said plurality of individual bit lines, and for generating a match signal when a serial bit pattern character received matches the plurality of individual bit lines. A means is provided for transferring the match signal from the preamplifier unit to the controller.

Polling a preamplifier within a disk drive to remotely determine pre-established parametric values

A disk drive comprising a plurality of read/write transducers, a programmable preamplifier, and a controller for furnishing control and data signals to the programmable preamplifier and for receiving data signals therefrom, is disclosed. The programmable preamplifier comprising a write data input circuit for receiving data signals to be supplied to a transducer, a read data output circuit for manifesting data signals supplied to said preamplifier unit by a transducer, and a transducer interface circuit for providing write data signals to a transducer and receiving read data signals from a transducer. The programmable preamplifier further comprises a multiplexer comprising a first multiplexer input connected to receive a first internal digital signal, a second multiplexer input connected to receive a second internal digital signal, a control input connected to receive a control signal for selecting between the first and second internal digital signals, and a multiplexer output for outputting the selected first or second internal digital signal. The multiplexer output is connected to an output terminal of the programmable preamplifier. The programmable preamplifier comprises a serial interface circuit for receiving serially presented control signals from the associated controller, including the control signal for selecting between the first and second internal digital signals.

Disk drive comprising a programmable preamplifier including a

A disk drive preamplifier unit includes a serial interface circuit for receiving serially formatted control signals from an associated disk drive controller. The control signals contain several types of information, including head select, write current magnitude, bias for MR transducers, gain magnitude for a variable gain amplifier, and test and mode information. The preamplifier unit incorporates several test circuits in addition to the usual write unsafe detector circuit, and a multiplexer controlled by the mode control signals from the serial interface unit is used to select which test circuit or detector is coupled to a common test output terminal whose signals are coupled back to the controller for further processing. The preamplifier can be used to remotely test the head population of the head disk assembly, to measure the MR bias current through any of the MR transducers and to signal the controller in response to polling characters when a match is obtained between a character and preestablished multi-bit parameter information fixed in the preamplifier unit. A write current generator is shared by the write transducers and the MR bias test circuit, with a current scaling unit used to provide different current ranges from the common source. The preamplifier unit affords remote control and testing which can be adapted to evolving systems using firmware changes alone.

Programmable preamplifier unit with serial interface for disk data

A format for embedded servo track identification fields in rotating disk data storage units such as magnetic disk drives. The present invention uses the concept of tri-bits (i.e., three code bits per logical bit) to encode track identification information in servo wedges of embedded servo disk drive systems. More specifically, two particular sets (and their equivalents) of tri-bit codes have been discovered to have optimum characteristics for providing a phase coherent encoding of a Gray code that is simple to translate into straight binary code. The properties of such tri-bit encoding limit error propagation to a single bit, which allows for very reliable track identification during movement of a head transducer across tracks (i.e., 'seeks'). A full range of Gray scale codes is available since more than two consecutive logical '0's can be reliably decoded when encoded using such tri-bits. The properties of such tri-bit encoding also allow for relatively high servo channel rates, which results in a reduction in servo field length. Accordingly, a counter-intuitive result of increasing the length of the encoding symbols for track identification fields is to decrease the overall length of the servo field, thereby permitting an increase in areal density.

Tri-bit encoding for disk drive servo track ID information

An integrated servo system for a disk drive employing sector servo positioning information on concentric tracks of a recording medium utilizes a servo burst pattern with three sequentially occurring servo bursts. One burst is positioned to have a maximum amplitude plateau on a track centerline of alternate tracks, and the other two bursts have maximum plateau values at locations between the centerlines of adjacent tracks. The amplitudes of the bursts are sequentially detected by a peak detector and supplied to sample and hold circuitry for measuring their relative amplitudes. Discriminator circuitry utilizes a window to provide two samples of each transition in the servo pattern and compares the samples to detect different fields and events in the pattern.

Information detecting system

A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip. An operational amplifier adaptable to this circuit is also disclosed.

Growing community of inventors

Irvine, CA, United States of America

Michael R Spaur