Apple Inc.

Intrinsity, Inc.

Evsx, Inc.

Michael R Seningen

James S Blomgren

Stephen C Horne

Terence M Potter

Michael E Runas

Ajay Bhatia

Anthony M Petro

Greg M Hess

Edward Martin McCombs, Jr

Vivekanandan Venugopal

Ben D Jarrett

Michael A Dreesen

Zhao Wang

Brian S Leibowitz

Mohamed Hassan Abu-Rahma

Andrew M Havlir

Robert D Kenney

Bo Yang

Raymond Cheung Yeung

Antonietta Oliva

David W Chrudimsky

Vijay M Bettada

Yi Zhao

Vasu P Ganti

Gregory D Roberts

Mihir S Sabnis

Sheela R Shreedharan

Siddhesh Gaiki

Asad A Bawa

Benjamin A Marrou

Christopher Ng

Zameeruddin Mohammed

James DeLeon

James De Leon

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

Memory bit cell for in-memory computation

An apparatus includes a plurality of circuit blocks, a plurality of scan-enabled flip-flop circuits, and a plurality of scan signature circuits. The plurality of scan-enabled flip-flop circuits may be coupled in a sequential manner across the plurality of circuit blocks, and be configured to shift a scan chain test signal from a test input interface to a test output interface. The plurality of scan signature circuits may be coupled to respective ones of a subset of the plurality of scan-enabled flip-flop circuits, and be configured to, in response to a particular test signal, concurrently load a known scan-chain pattern to the subset of the scan-enabled flip-flop circuits. The plurality of scan-enabled flip-flop circuits may be further configured to sequentially output at least a portion of the known scan-chain pattern to the test output interface.

Scan chain analysis using predefined capture signature

A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

System control using sparse data

A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.

Data pattern based cache management

A system and method for efficiently handling voltage level shifting are contemplated. In various embodiments, a first level shifter receives a first isolate enable signal based on a first power supply voltage and a second isolate enable signal based on a second power supply voltage different from the first power supply voltage. A second level shifter generates the first isolate enable signal based on both the second isolate enable signal and the first power supply voltage. A circuit block generates a data signal based on the first power supply voltage. When it is determined that isolation for the first level shifter is enabled, the first level shifter generates a voltage level on an internal particular node to a particular voltage level based on the first isolate enable signal, and also prevents, using the second isolate enable signal, the data signal from setting a voltage level on the particular node.

Level shifter with isolation on both input and output domains with enable from both domains

A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.

Output signal control during retention mode operation

An electronic circuit is disclosed. A first flip-flop is coupled to receive a clock signal from clock gating circuit. The first flip-flop includes an input circuit having a data input, a master-slave latch, and an output circuit. Responsive to an edge of the clock signal, the master-slave latch may latch a logic value of a signal received on the data input. The output circuit is coupled to the master-slave latch, and provides a logic output signal corresponding to the logic value latched by the master-slave latch. The clock gating circuit may provide one or more inversions of the clock signal which it receives. The flip-flop provides no inversions of the clock signal.

Flop circuit with integrated clock gating circuit

A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.

Low power clock gating circuit

An apparatus for detecting a change in a voltage level of a power supply is disclosed. An inverter coupled to a first power supply may generate a signal dependent upon a voltage level of a second power supply. A latch coupled to the first power supply may be set based on a first voltage level of the second power supply and a first value of the signal, and re-set based on a second voltage level of the second power supply and a second value of the signal different than the first value of the signal.

Power detection circuit

An apparatus and method for operating a level shifter circuit that receives an input signal of interderminate voltage level is disclosed. The level shifter circuit may receive the input signal from a circuit block coupled to a first power supply signal, and generate an output signal using a second power supply signal, different than the first power supply signal. The level shifter circuit may clamp a storage node included in the level shifter circuit, and isolated at least one circuit path included in the level shifter circuit in response to a determination that an isolation signal has been enabled.

Level shifting circuit with data resolution and grounded input nodes

Growing community of inventors

Austin, TX, United States of America

Michael R Seningen