International Business Machines Corporation

Michael R Scheuermann

Jean-Marc Halbout

Matthew R Wordeman

Ernest Bassous

Rajiv V Joshi

Pradip Bose

Paul Andrew Moskowitz

Subramanian Srikanteswara Iyer

Eren Kursun

Michael Stephen Floyd

Joel Abraham Silberman

Frank Daniel Egitto

Gary Dale Carpenter

David Brian Stone

Alfred Viehbeck

Stephen L Buchwalter

James Douglas Warnock

Phillip John Restle

Martin J Goldberg

Christopher J Berry

Mark B Ketchen

Michael H Wood

Natalie Barbara Feilchenfeld

Arun Joseph

Leon Jacob Sigal

Elizabeth F Foster

Stephen L Tisdale

Kurt R Grebe

Stephen Joseph Fuerniss

Linda C Matthew

Caroline A Kovac

Sungjae Lee

Nagashyamala R Dhanwada

Shih-Hsien Lo

James Steven Kamperman

Michael Alexander Bowen

Gobinda Das

Arjen Alexander Mets

Walter P Pawlowski

Michael P Beakes

John J Glenning

Mark J Schadt

Eugene Shapiro

Donald J Mikalsen

William W Dungan

Herbert P Byrnes

Vijay P Kesan

William A Donson

Richard A Wachnick

Massimo A Ghioni

A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner&#x2014;based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

Early analysis and mitigation of self-heating in design flows

A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

Vertical power budgeting and shifting for three-dimensional integration

There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.

Configuration of connections in a 3D stack of integrated circuits

There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

3D inter-stratum connectivity robustness

A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

Process for managing complex pre-wired net segments in a VLSI design

Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.

Gray scale etching for thin flexible interposer

Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity. The interdigitated pattern is then etched through the oxide film by lithography to expose the Si surface and metallic electrode members are formed selectively in the exposed Si surface, using self-aligned metallization to produce thin interdigitated electrodes recessed below the silicon surface, which itself may be on a comparatively thin Si layer. The electrodes may be spaced to minimize the interdigital carrier transit time and maximize the sensitivity and the entire process and structure are compatible with conventional silicon integrated circuit (IC) technology. A further feature involves isolating the semiconductor surface layer from the substrate by a layer that may be either 1) transparent and insulating, 2) optically absorbing, or 3) optically reflecting, so that the photocarriers recombine before they can be collected by the field. In the latter case, the photodetector acts as a resonant cavity, resulting in an increase in the number of carriers that are generated, and hence a more sensitive device.

High speed silicon-based lateral junction photodetectors having recessed

Certain organic polymeric materials are capable of reversibly accepting or donating electrons from a reducing entity. The redox sites in the polymer accept electrons and, as a result, a change in the properties of the polymer occurs. This change is useful in modifying or etching the polymeric material The material can be modified by incorporation of metallic seeds into the material at a controlled depth. The seeds are incorporated by interaction of cations of the metals with the redox sites in the polymer, which cause the reduction of the cations to form the neutral metallic seeds. Subsequent exposure of the polymeric material containing the seeds to an electroless bath causes further deposition of metal having the desirable characteristic of good adhesion to the polymeric material. Etching of the polymeric material can be carried out as a result of an increase in solubility of the polymer in aprotic solvents when its redox sites have accepted electrons. The increased solubility allows openings to be etched in certain areas of the polymeric material that have been reduced, leaving other areas unchanged.

Method for conditioning an organic polymeric material

A thin interface pellicle probe for making temporary or permanent interconnections to pads or bumps on a semiconductor device wherein the pads or bumps may be arranged in high density patterns is described incorporating an electrode for each pad or bump wherein the electrode has a raised portion thereon for penetrating the surface of the pad or bump to create sidewalls to provide a clean contact surface and the electrode has a recessed surface to limit the penetration of the raised portion. The electrodes may be affixed to a thin flexible membrane to permit each contact to have independent movement over a limited distance and of a limited rotation. The invention overcomes the problem of making easily breakable electrical interconnections to high density arrays of pads or bumps on integrated circuit structures for testing, burn-in or package interconnect and testing applications.

Thin interface pellicle for dense arrays of electrical interconnects

A testing or sampling probe to determine the response of electrical circuits or devices to ultrafast electrical pulses. The probe is detachable from the device being tested. The probe includes a transparent substrate though which optical pulses are focused or directed onto a photoconducting gap. The probe further includes a transmission line associated with the photoconductive gap, and which terminates at a tapered end of the probe in contacts which are placed on the device under test.

Detachable high-speed opto-electronic sampling probe

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Katonah, NY, United States of America

Michael R Scheuermann