Unisys Corporation

Michael R Overley

Larry L Byers

Lloyd E Thorsbakken

Gary R Robeck

Jerome G Carlin

A method of and apparatus for improving the efficiency of a data processing system employing multiple busses operating at multiple data transfer rates. Each of the multiple physical busses has its own characteristics including maximum data transfer rate, parallel word width, etc. Two or more of these physical busses are combined into a single logical bus, wherein the single logical bus has characteristics resulting from the combination of physical busses. These characteristics can include greater parallel word widths, enhanced maximum data transfer rates, etc.

Logical PCI bus

An improved fault detection system and method for detecting the occurrence of faults within the addressing logic of a storage device is provided. Data stored to a selected address within a storage device includes a copy of the selected address. During a subsequent read operation, the copy of the address is read from memory and compared to the read address used to perform the memory access. If the addresses are not the same, a potential addressing fault occurred within the control logic of the storage device. The fault detection system is particularly adaptable for use with storage devices having a relatively small number of addressable locations, each containing a relatively large number of bits. According to one embodiment of the invention, the storage device is a General Register Array (GRA) utilized as a queue.

System and method for detecting faults in storage device addressing logic

A response stack validation checking circuit for providing a hardware based approach for monitoring the integrity of a read and a write pointer in a memory stack. The present invention may be utilized in systems having a common memory controller for controlling the read and write pointers or a system having a number of asynchronous memory controllers, wherein each controller controls a different pointer. The present invention allows the memory controller elements to be less complex than a software based approach and therefore may reduce the physical space and power required by the memory controllers. Finally, the present invention may monitor the integrity of the read and write pointers in parallel with the memory controllers and in real time thereby not slowing down system performance.

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Maple Grove, MN, United States of America

Michael R Overley