Sigmatel, Inc.

Motorola Corporation

Silicon Laboratories Inc.

Skyworks Solutions, Inc.

Freescale Semiconductor,inc.

Vixs Systems, Inc.

Other

Corning Research & Development Corporation

Vixs, Inc.

Michael R May

Patrick De Bakker

Mathew A Rybicki

Michael David Cave

Carlos Jesus Briseno-Vidrios

Matthew Derrell Felder

Erich Lowe

Fernando Naim Lavalle Aviles

Matthew A Pendleton

Jon David Hendrix

Marcus William May

Péter Onódy

Tamás Marozsák

Terence L Johnson

Timothy W Markison

Russell Croman

Charles Guo Lin

Dan Bernard Kasha

Javier Elenes

James Ward Girardeau, Jr

Brian Douglas Green

Carlos A Greaves

Howard E Levin

Thomas Glen Ragan

Peter R Molnar

Gabor Marek

Michael Johnson

Paul M Astrachan

Matthew Brady Henson

Scott Thomas Haban

Lawrence Ragan

Andras V Horvath

Nebojsa Stanic

John E Willis

John M Khoury

Donald Kent Larson

Alessandro Piovaccari

David S Trager

Ramin Khoini-Poorfard

Junsong Li

Frederick Rush

Peter Vancorenland

Takaya Yamauchi

Younes Djadi

Jing Li

Alan F Hendrickson

Mitchell Reid

Pio Balmelli

András Vince Horváth

Joseph Christopher Sawicki

Pascal Blouin

James Girardeau

James Robert Kelton

James Doyle

David Le Goff

Sujit Sudhaman

Jeffrey P Gleason

Chunyu Xin

Rex Tak Ying Wong

Raymond L Vargas

Henry William Singor

Joseph C Fong

Qi Cai

Christopher S Gregg

Shawn Saleem

Jody H Everett

Jean-Marc Guyot

John M Porter

Robin Wiprud

Dave Baker

Jingyu Hu

Jamie Joseph Happ

Anselmo Pilla

An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.

Demodulator for an isolation communication channel for dual communication

An isolated gate driver includes a first input terminal to receive gate information and one or more input terminals to receive configuration information. A modulation circuit generates a modulated signal having four possible states, each of the four possible states corresponding to a different unique pair of values of the gate information and the configuration information. The modulation circuit represents two of the states using on-off keying (OOK) while the configuration information is at a first value and represents two of the states as a modification to the OOK modulation based on the configuration information being at a second value. The modulated signal is sent over an isolation communication channel coupling a transmitter and receiver of the isolated gate driver.

Transmitter for dual communication over an isolation channel

An isolated gate driver has a first portion in a first voltage domain and a second portion in a second voltage domain. The first and second portions are coupled by an isolation communication channel. The isolated gate driver transmits across the isolation communication channel a serial word containing first drive strength information and simultaneously transmits gate information with the serial word across the isolation communication channel. The gate information indicates a state of a gate signal for a transistor coupled to the second portion of the isolated gate driver. A demodulator circuit demodulates a signal containing the gate information and the drive strength information transmitted across the isolation communication channel in the serial word. A gate signal output circuit coupled to the demodulator circuit supplies the gate signal based on the gate information with a drive strength of the gate signal being based on the drive strength information.

Interface for passing control information over an isolation channel

A method for protecting a system including a driver integrated circuit includes receiving a driver input signal. The method includes driving an output signal externally to the driver integrated circuit. The output signal is driven based on the driver input signal and an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node coupled to a terminal of the driver integrated circuit.

Gate driver output protection circuit

In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Mode selection circuit for low-cost integrated circuits such as microcontrollers

A scan controller provides a translation between a two terminal external interface and a four signal line internal scan interface to a digital core of the integrated circuit. The two terminal external interface has an input terminal and an input/output terminal. The input terminal receives a clock signal and the input/output terminal serially receives a scan enable signal and a scan in data bit. A state machine controls the scan controller. The scan in data bit, the scan enable signal, and a scan clock signal are supplied in parallel to the internal scan interface. The digital logic provides a scan out data bit and the scan controller supplies the scan out data bit over the input/output terminal in synchronism with the clock signal.

Two pin scan interface for low pin count devices

A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.

Low power heartbeat for low power mode

An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.

Isolator with symmetric multi-channel layout

An optical connector having at least one removable integrated assembly tool for terminating an optical fiber cable is described. The connector comprises a housing configured to mate with a receptacle, a collar body disposed in the housing, a backbone that retains the collar body in the housing, a removable funnel-shaped and a fiber boot. The collar body secures a ferrule secured at a first end thereof, and includes mechanical element disposed in an intermediate portion and a buffer clamping portion near a second end of the collar body. The backbone has a mounting structure surrounding a central bore at one end. The funnel-shaped fiber guide attaches to the mounting structure to facilitate insertion of an optical fiber into the connector, and wherein the fiber boot is attachable to the mounting structure after the fiber guide has been removed.

Optical fiber connector with integrated installation tools

Growing community of inventors

Austin, TX, United States of America

Michael R May