At&t Bell Laboratories

Michael R Lundberg

Sanford S Brown

Dennis J Hunsberger

There is disclosed an interrupt arrangement for use in a multiprocessing system where it is desired to specifically direct interrupts from one processor to any other processor. The arrangement treats the interrupt signal as a data communication between processors. In this regard, common address space is set aside, on a system basis, for interrupt signals. A sending processor first contends for the system bus and then addresses a message to a specific target processor. The message is received at the target processor over the regular communication channel and stored in a FIFO memory. Interrupt messages filter through the memory in order of arrival and cause interrupts to occur at the target processor. The information at the output of the FIFO memory controls the processing of the interrupt.

Growing community of inventors

Bridgewater, NJ, United States of America

Michael R Lundberg