International Business Machines Corporation

Michael R Kelly

Mark Alan Erle

Eli M Dow

Harry Roger Kolar

Steven R Carlough

Jessie Yu

Michael L Passow

Embodiments of the invention are directed to computer-implemented methods, computer systems, and computer program products for remote monitoring of devices. The method includes causing a launch of an unmanned aerial vehicle (UAV). The UAV is instructed to fly a path that is optimized to read optical signals from a set of one or more devices. Data is received from the UAV, the data corresponding to the optical signals read from the set of one or more devices.

Remote sensor monitoring using LED transmission

A computer-implemented method includes arranging two or more sensor nodes into a ring monitor. Each sensor node of the ring monitor is coupled to a sensor and cross-monitors at least one other sensor node in the ring monitor. A request is received to add a new sensor node. A spatial partitioning of a plane is generated, by a computer processor, representing locations of the new sensor node and the two or more sensor nodes in the ring monitor. The spatial partitioning includes a plurality of regions, each region corresponding to a sensor node. Two or more adjacent sensor nodes are selected from the two or more sensor nodes in the ring monitor, based at least in part on the spatial partitioning. The two or more adjacent sensor nodes are instructed to monitor the new sensor node, which is instructed to monitor each of the two or more adjacent sensor nodes.

Ring-based monitoring of sensor mesh networks

Error detection using parity compensation in binary coded decimal (BCD) and densely packed decimal (DPD) conversions, including a computer program product having a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving formatted decimal data in a first format, the formatted decimal data consisting of a DPD format data or a BCD format data. One or more first parity bits are generated by converting the received data into a second format of the formatted decimal data, and by determining the parity of the data in the second format. One or more second parity bits are generated directly from the received data. An error flag is set to indicate an error in the data in the second format in response to the first parity bits not being equal to the second parity bits.

Error detection using parity compensation in binary coded decimal and densely packed decimal conversions

A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are generated. The subvector leading-zero counts are biased by a constant amount. Next, one or more prefix bits are calculated. Finally, at least a portion of a selected subvector leading-zero count is concatenated to the prefix bits to yield a total leading-zero count for the binary vector.

Method and apparatus for binary leading zero counting with constant-biased result

A method and circuit for summing multiples vectors is disclosed. The method includes receiving a set of input vectors and generating a set of decoded summation vectors. Each of the set of decoded summation vectors indicates the value of at least a portion of the vector sum. The method further includes generating a set of decoded carry vectors. Each carry vector is used to select the summation vector for an adjacent portion of the vector sum from a set of preliminary summation vectors. In one embodiment, the method further includes counting the number of high bits in each bit position of the input vectors and generating decoded high bit count vectors based upon the counting to facilitate the generation of decoded summation vectors. In one embodiment, the set of preliminary vectors includes an initial preliminary summation vector and a set of adjacent summation vectors. In this embodiment each adjacent summation vector is achieved with a 1-bit rotation of the preceding adjacent summation vector. In another embodiment, the invention contemplates a method of adding multiple binary vectors in which a first decoded summation vector indicative of a first portion of a vector sum is generated and a first decoded carry vector indicative of the carry from a first portion of the vector sum is generated. An initial second decoded summation vector corresponding to a second portion of the vector sum is then generated and a set of preliminary summation vectors generated from the initial second summation vector. Each of the preliminary summation vectors is rotated by one bit position from the adjacent vectors in the set of preliminary summation vectors. One of the set of preliminary summation vectors is then selected as the second summation vector based upon the value of the first carry vector. In one embodiment, the value indicated by the first carry vector indicates the number of times the selected second summation vector was rotated from the initial summation vector.

Growing community of inventors

Wappingers Falls, NY, United States of America

Michael R Kelly