Micrel, Incorporated

Michael R Hsing

Martin E Garnett

James Copland Moyer

Martin J Alter

Helmuth R Litfin

A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated, thus avoiding/simplifying fabrication steps, conserving die area, and allowing increased component density.

Self-alignment technique for forming junction isolation and wells

A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

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San Jose, CA, United States of America

Michael R Hsing