Ncr Corporation

Michael R Hilley

William J Kass

Gene F Young

Craig A Walrath

Terry S Strickland

Lee W Hoevel

Kim B Cannon

B Russell Bryan

A system for providing test tools at a remote location with a portable computer is disclosed. The system includes a peripheral interface coupled to the computer for communicating data between the computer and a unit under test. The test tool is implemented on a printed circuit card that, preferably, conforms to the dimensions and specifications of the card categories for the Personal Computer Memory Card Interface Association (PCMCIA) standard. The test tool receives and transmits signals to and from the unit under test so that an application program executing within said computer may display, analyze, or otherwise use the data received from the test tool which is controlled by the program. The test tool includes a tuple to identify the functionality of the tool. A card service interpreter within the computer communicates with the tool in accordance with the tuple information identifying the test tool.

Integrated test tools for portable computer

A method for controlling access to a memory includes the step of defining a group of priority codes, each of which represents an order for granting simultaneous memory access requests. One of the group of priority codes is selectively provided to a memory controller. A request to access memory is then granted according to the selected priority code.

Method for prioritizing memory access requests using a selected priority

In computers, a test of memory is generally performed at the time of powering up. In one form of the invention, this type of test is run on part of Random Access Memory (RAM), while allowing data or a program to reside in another part. Then, after the partial test is completed, the data is transferred into the RAM just tested, and the RAM which previously held the data is tested. Thus, the data can co-exist in memory while the test runs, by being shuttled from one location to another.

Non-destructive memory testing in computers

A method and system of maintaining coherency for a data block transferred from a main memory to a cache memory. The data transfer is recorded in a tag register in the main memory. An overwrite of the data block is detected by comparing main memory data writes with the recorded transfer. The cache memory is only notified in the event an overwrite is detected. An invalid flag is then set in the cache.

Method and system for maintaining data coherency between main and cache

A system and method for requesting access to refresh a computer memory. Two lines are connected between a timer and arbiter. A memory refresh request signal is provided on the first line and is accorded a relatively low priority by the arbiter. If the first request is not granted within a predetermined period of time, a second memory refresh request signal is provided on the second line and is accorded a relatively high priority by the arbiter.

System and method for requesting access to a computer memory for

In a computer, when a block of data is written to memory, it is common to attach a control word to the data. The control word is placed at a pre-arranged location, generally separate from the data. The control word contains important information about the data, such as starting address, length, etc. The presence of the control word indicates that the data is valid. Sometimes, for various reasons, the control word is written before all the data is written. This premature availability of the control word gives false information: the data is not yet completely written, yet the presence of the control word indicates otherwise. The invention prevents such a problem by preventing premature writing of the control word.

Method and apparatus for storing a data block in multiple memory banks

A system comprising a memory for transferring m data bytes at a time, first and second busses each having a width of less than m data bytes, first parallel m byte wide read and write registers connected between the first bus and the memory and second parallel m byte wide read and write registers connected between the second bus and the memory.

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Belton, SC, United States of America

Michael R Hilley