Quickturn Design Systems, Inc.

Altera Corporation

Other

Nethra Imaging Inc

Cadence Design Systems, Inc.

Mentor Graphics Corporation

Quickturn Design

Michael R Butts

Stephen Paul Sample

Rakesh H Patel

Kevin A Norman

Jon A Batcheller

Chao Chiang Chen

Mikhail Bershteyn

Jerry R Bauer

Anthony Mark Jones

Elliot H Mednick

Ming Yang Wang

Alon Kfir

Paul M Wasson

Swey-Yan Shei

Embodiments of the invention are directed to a system for reconfiguring a processor array while it is currently operating. The reconfiguration system uses configuration chains streamed down communication channels that are set for the re-configuration process, then re-set after the reconfiguration process has completed.

System for reconfiguring a processor array

This disclosure relates to a system of communicating, data within an integrated circuit. Multiple components, or channels, can share common physical communication lines between elements within the system. In some aspect, only one component can access the physical lines at a given time and a selection device chooses which component is active on the physical lines and makes the appropriate connection to the lines. The selection and connection can be completed without requiring or reporting information to the components, and is thus transparent.

System of virtual data channels in an integrated circuit

A design verification system for developing electronic systems and methods for manufacturing and using same. The design verification system comprises a plurality of system elements, including at least one physical (or hardware) element and/or at least one virtual (or software) element, which are coupled, and configured to communicate, via a general communication system. Since the system elements may be provided on dissimilar development platforms, each system element is coupled with the communication system via a co-verification interface, which is provided as a layered protocol stack to assure portability and flexibility. Through use of the co-verification interface, the design verification system can be configured to support a wide variety of mixed physical/virtual systems.

System and method for performing design verification

A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

Emulation system with time-multiplexed interconnect

A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Logic multiprocessor for FPGA implementation

A programmable logic device architecture. This programmable logic architecture includes a first logic block () containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (), which interfaces with the first logic block (), for performing JTAG functions, configuring the first logic block (), initializing the first logic block (), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block () may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (). The first logic block () includes a plurality of second logic blocks () which may be programmably coupled using a second programmable interconnect network (). The second programmable interconnect network () may be programmably coupled to the first programmable interconnect network (). Furthermore, the plurality of second logic blocks () include a plurality of third logic blocks () which may be programmably coupled using a third programmable interconnect network (). A signal from a third logic block () may be programmably coupled to the other logic blocks, the diagnostic block interface (), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

High-performance programmable logic architecture

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Memory circuit for use in hardware emulation system

A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic.

Optimized emulation and prototyping architecture

A programmable logic device architecture. This programmable logic architecture includes a first logic block ( ) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface ( ), which interfaces with the first logic block ( ), for performing JTAG functions, configuring the first logic block ( ), initializing the first logic block ( ), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block ( ) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network ( ). The first logic block ( ) includes a plurality of second logic blocks ( ) which may be programmably coupled using a second programmable interconnect network ( ). The second programmable interconnect network ( ) may be programmably coupled to the first programmable interconnect network ( ). Furthermore, the plurality of second logic blocks ( ) include a plurality of third logic blocks ( ) which may be programmably coupled using a third programmable interconnect network ( ). A signal from a third logic block ( ) may be programmably coupled to the other logic blocks, the diagnostic block interface ( ), and other circuitry on the integrated circuit. The internal circuitry of these logic blocks may be monitored through a variety of programmable interconnect paths. This architecture is useful when debugging a design, especially for emulation and prototyping applications.

A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Programmable logic device having integrated probing structures

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.

PLD with on-chip memory having a shadow register

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (&ldquo;FPGA&rdquo;), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

FPGA with on-chip multiport memory

A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (&ldquo;FPGA&rdquo;), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

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Portland, OR, United States of America

Michael R Butts