Sony Corporation

Sony Trans Com Inc.

Other

Michael R Atkinson

Dilip C Shah

Dale I Havens

Daniel A Lotocky

James Bruce Whitehouse

Kaz Takata

Russell Auerbach

Kouwei Shen

Troy D Batterberry

A method to update information including code and data in a non-volatile memory reliably and efficiently to avoid loss of information during the loading process and to minimize aircraft service downtime in an In-Flight Entertainment System (IFES). The non-volatile memory is partitioned into two sections: one section contains the currently valid information and the other is available for loading the new information. A section pointer is used to keep track of the currently valid section and to select the loading section. The new information is loaded to the selected loading section. A validation procedure is performed to determine if the loading is successful. When the loading of the new information is successfully completed, the section pointer is updated to point to the newly loaded section.

Method and apparatus for efficient software updating

An indexing system for signs consisting of a plurality of indicia bearing vane faces wherein the vane faces are sequentially exposed to view in the manner of a 'wave', such sequential revealing of the sign vane faces generating interest in the sign's message. Each sign vane is rotated by a transmission and the transmissions are interconnected in such a manner as to sequentially operate the vanes to produce the 'wave' action and detents associated with each transmission lock the sign vane in the desired position.

Indexing system for changeable signs

A communication subsystem used in an aircraft entertainment system employs a microcontroller and a dual-ported RAM to relieve burden from the host processor in handling low-level operations in communicating with external devices. The host processor and the microcontroller accesses the dual-ported RAM by testing the semaphore to determine if the DPRAM is available. If available, the processor and/or the microcontroller will read/write the messages from/to the DPRAM as appropriate. The microcontroller controls the communication interface controllers directly and will send messages read from the DPRAM to the CICs or write to the DPRAM messages received from the CICs without host processor's intervention. The microcontroller also performs other low-level operations such as header/trailer processing and error checking/correcting free from the host processor.

Efficient message processing using a multi-ported RAM and a dedicated

Implemented on a vehicle, a digital in-transit entertainment system that assists in providing passenger services to a plurality of end nodes of a vehicle. The system includes a multi-drop digital communication bus, preferably configured to support RS-485 standards. A plurality of zone bridge units ('ZBUs') and a system manager unit ('SMU') are coupled to the digital communication bus. At least one ZBU is responsible for signaling headend equipment to perform a requested passenger service. The SMU is also designed to signal another type of equipment if implemented in lieu of the first type. Both the ZBUs as well as the SMU are designed to contain PSS status information for every end node of the vehicle to maintain coherency.

System and method for processing passenger service system information

A system and method for multiple processors operating independently from one another to share memory as a boot device. The system includes a plurality of computing systems each including a processor and a local memory element. In response to a boot condition for a selected computing system, its processor begins a boot sequence in which it uses operational code contained within a non-volatile memory element that is shared by each of the computing systems. Arbitration for ownership of a memory bus interconnecting the non-volatile memory element to the processors and organization of a direct memory access transfer between the non-volatile memory element and local memory associated with the processor of the selected computing system is controlled by a memory access coordination circuit coupled between the computing systems and the memory bus.

System and method for sharing a non-volatile memory element as a boot

The interrupt regenerator circuit converts the transition signal caused by a passenger's data entry in an aircraft entertainment system into a triggering signal. The triggering signal triggers a delay element consisting of cascadable one-shot devices. The timing intervals for the outputs of these one-shot devices are programmable through the selection of proper values for the resistors and capacitors. The interrupt signal is de-asserted by the host processor when the host processor responds to the interrupt. The delayed interrupt signal is then gated by the interrupt signal itself to regenerate the interrupt signal to the host processor.

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Irvine, CA, United States of America

Michael R Atkinson