Broadcom Corporation

Sitrus Technology Corporation

Inphi Corporation

Other

Avago Technologies International Sales Pte. Limited

Conexant Systems, Inc.

Michael Q Le

Howard A Baumer

Aaron W Buchwald

Hui Wang

Xicheng Jiang

Avanindra Madisetti

Karim Vincent Abdelhalim

Myles H Wakayama

Jurgen Van Engelen

Jorge Pernillo

Kevin Tunghai Chan

Mrunmay Talegaonkar

Chun-Ying Chen

Halil Cirit

Pieter Vorenkamp

Jamal Riani

James Lawrence Gorecki

Karthik S Gopalakrishnan

Hui Pan

Guojun Ren

Irene Quek

Chang-Feng Loi

Belal Helal

Haidang Lin

Amber Tan

John S Wang

Chung-Jue Chen

Kwang Young Kim

Gavin Derek Parnaby

Josephus A Van Engelen

Seong-Ho Lee

Umesh Sharma

Josephus Van Engelen

Srinjoy Das

Shyam Krishnamurthy

Surya S Bhattacharya

Wynstan Tong

Jorge Antonio Casanova

Frank Van Gieson

Raymond L Clancy

An H-bridge integrated laser driver optimizes power dissipation, impedance matching, low-swing and high-swing reliability for electro-absorption modulated laser (EML) and directly modulated laser diode (DML) applications. The laser driver includes a retimer for converting low-speed parallel data to a high-speed serial bit stream and to an inverted representation of the high-speed parallel bit stream, an M-bit PMOS DAC configured to receive a first buffered bit stream, an N-bit NMOS DAC configured to receive a second buffered bit stream substantially synchronized with the first buffered bit stream. A protective device is coupled between the M-bit DAC and the N-bit DAC. A first DC level-shifting predriver array is coupled between the retimer and the M-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream, and a second DC level-shifting predriver array is coupled between the retimer and the N-bit DAC to receive the high-speed parallel bit stream and the inverted high-speed parallel bit stream. An impedance matching module is coupled to an output of the protective device. The laser driver may be integrated on a CMOS communication chip.

H-bridge integrated laser driver

A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency. In subsequent iterations, proportional feedback to the DCO of lower rate sums of symbol streams is combined with integral feedback of codes representing finer approximations of the unknown data frequency swept over successively narrowing bands, and the DCO is locked to the finest approximation that lies between consecutive codes corresponding to sums having opposite signs.

Referenceless frequency acquisition

An ADC system dynamically adjusts threshold levels used to resolve PAM signal amplitudes into digital values. The ADC circuitry includes an analog front end to receive and condition the PAM signal, a low-resolution ADC to digitize the conditioned signal according to a first set of threshold values, and a high-resolution ADC to subsample the conditioned signal to generate subsampled signals. A microprocessor in communication with the low-resolution ADC and the high-resolution ADC derives a statistical value from the subsampled signals, determines an updated set of threshold values, and dynamically replaces the first set of threshold values for the low-resolution ADC with the updated set of threshold values.

ADC having adjustable threshold levels for PAM signal processing

A method to implement hybrid signal processing includes steps for receiving an analog signal at a receiver frontend, sampling the received analog signal and storing the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend. Then, processing the plurality of analog sampled signals using interleaved feed-forward equalizers (FFEs) to provide FFE interleaved sampled signal values corresponding to each of the sampling circuitries. Then, processing the analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain DFE interleaved sampled signal values, summing each of the FFE interleaved sampled signal values with output from one of the DFE interleaved sampled signal values to provide equalizer output signal values, and digitizing the equalizer output signal values to provide digital data bits corresponding to each of the equalizer output signal values. Implementations of the method as a hybrid communication system, system-on-a-chip, and computer readable memory are also disclosed.

Methods, systems and apparatus for hybrid signal processing for pulse amplitude modulation

A DC-shifting predriver has an input port configured for coupling to a serial data stream, an inverting output amplifier having an feedback node and an output port configured for coupling to a transistor at the input to a high-speed DAC or TX driver, and a capacitor AC-coupled between the input port and the feedback node. A weak feedback inverter having structure similar to, but less drive strength than the inverting output amplifier is coupled between the output port and the feedback node to act as a positive feedback latch. The predriver provides a DC shift up to 3V with high reliability and minimal intersymbol interference for data rates from 10 GS/s to 28 GS/s or higher. The predriver may provide multiple input ports implemented as a predriver array in an M-bit system, and the output amplifier may consist of N stages.

High-speed DC shifting predrivers with low ISI

The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.

CMOS externally modulated laser driver

The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.

Equalization for transmitter input buffer array

Methods, systems, and apparatuses, including electrical circuitry, are described for auto-negotiation. Active cables, active backplanes, and line cards may include one or more instances of electrical circuitry and/or integrated circuits that intercept advertisements of standard auto-negotiation protocol signaling from an initiating device for establishment of communication links with a receiving device. Auto negotiation information in the intercepted signaling may be translated and encoded into signaling in accordance with the capabilities of the receiving device. Active cables and active backplanes may also include one or more connection components between instances of electrical circuitry and/or integrated circuits to provide high-speed transmission of data packets encapsulating the auto-negotiation information in a format that differs from the standard auto-negotiation protocol.

Apparatus, system, and method for auto-negotiation

In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Interleaved successive approximation register analog to digital converter

Growing community of inventors

Laguna Niguel, CA, United States of America

Michael Q Le