International Business Machines Corporation

Other

Motorola Corporation

Michael Putrino

Soummya Mallick

Stamatis Vassiliadis

Lee Evan Eisen

Brice J Feal

Ann E Huffman

Gerald George Pechanek

Christopher Hans Olson

Rajesh Bhikhubhai Patel

Romesh Mangho Jessani

Albert John Loper

Robert Thaddeus Golla

Eric M Schwarz

James Allan Kahle

David Allen Hrusecky

Charles P Roth

Agnes Yee Ngai

Huy Van Nguyen

Thomas Elmer

Timothy A Elliott

Aubrey Deene Ogden

Albert J Loper, Jr

Sung-Ho Park

Tai Dinh Ngo

Eric M Schwartz

Johm Victor Sell

Rajesh Bikhubhai Patel

A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.

Saturation select apparatus and method therefor

A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a plurality of multiply structures, each containing only a single multiply array, that each correspond to at least one element of a vector input operand. Utilizing the single multiply array, each of the plurality of multiply structures is capable of performing a multiplication operation on one element of a vector input operand and is also capable of performing a multiplication operation on multiple elements of a vector input operand concurrently. In an embodiment in which the maximum length of an element of a vector input operand is N bits, each of the plurality of multiply arrays can handle both N by N bit integer multiplication and M by M bit integer multiplication, where N is a non-unitary integer multiple of M. At least one of the multiply structures also preferably includes an accumulating adder that receives as a first input a result produced by that multiply structure and receives as a second input a result produced by another multiply structure. From these inputs, the accumulating adder produces as an output an accumulated sum of the results in response to execution of the same instruction that caused the multiply structures to produce the intermediate results.

Processor having vector processing capability and method for executing a vector instruction in a processor

A mechanism structured to check for instruction collisions at the Dispatch Unit rather than the Completion Unit. In processors which issue multiple commands simultaneously, a flag bit is sent to the Completion Unit and attached to the instruction in the queue that follows the other in program order if they both have the same targeted address. When the instructions from position 1 and position 2 of the instruction queue are ready to issue, the Completion Unit checks position 2 for a flag bit. If there is a bit, then the instruction in position 1 is discarded and the instruction in position 2 is written to the target address. If there is no flag bit with the instruction in position 2, the instruction in position 1 is written to the target register. This method eliminates the need to compare all the targeted addresses that are associated with the rename registers. It requires two comparisons instead of a minimum of 15 comparisons.

System for completing instruction out-of-order which performs target

A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

Processor and method for out-of-order execution of instructions based

A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution. In response to a determination that n instructions cannot be dispatched during the first processor cycle, a determination is made whether a fixed point instruction is available to be dispatched and whether dispatching the fixed point instruction to the non-FXU for execution will result in greater efficiency. In response to a determination that a fixed point instruction is not available to be dispatched or that dispatching the fixed point instruction to the non-FXU will not result in greater efficiency, dispatch of the fixed point instruction is delayed until a second processor cycle. However, in response to a determination that dispatching the fixed point instruction to the non-FXU will result in greater efficiency, the fixed point instruction is dispatched to the non-FXU and executed, thereby improving execution unit utilization.

Method and apparatus for executing fixed-point instructions within idle

A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is executed by concatenating a suffix to the mantissa in the single-precision floating-point register and replacing the high-order bit of the exponent with a prefix selected as a function of the high-order bit, wherein the resulting mantissa and exponent form a double-precision floating-point number that is then stored to memory. A load-float-double instruction is executed by dropping the suffix from the mantissa of the double-precision floating-point number in memory, and replacing the prefix with the high-order bit, wherein the resulting mantissa and exponent form a single-precision floating-point number that is then loaded into the single-precision floating-point register.

Load-store unit and method of loading and storing single-precision

The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.

Method and apparatus for dynamic allocation of registers for

A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A second aspect provides a fast calculation of a function of the guard bit. Both aspects comprise means for providing an intermediate result of a floating point mathematical operation involving at least a first and a second operand and means for providing a mask indicating a position of a leading one in a mantissa of the intermediate result. In the first aspect, means for aligning a first bit of the mask to an (n+2)nd bit of the intermediate result, where n is the number of bits in a mantissa of the first or second operand, are coupled to the intermediate result providing means. In the second aspect, means for aligning a first bit of the mask to an (n+1)st bit of the intermediate result are coupled to the intermediate result providing means. In both aspects, means for providing an output are coupled to the aligning means and intermediate result providing means. The output of the first aspect comprises the sticky bit. The output of the second aspect comprises a function of the guard bit. Thus, the method and system allow the sticky bit and a function of the guard bit to be calculated substantially simultaneously with normalization. Because the method and system allow fast determination of the sticky bit and a function of the guard bit, the overall speed of the calculation is increased and system performance is improved.

Method and system for fast determination of sticky and guard bits

A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

Method for implementing a four-way least recently used (LRU) mechanism

A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.

Instruction dispatch queue for improved instruction cache to queue timing

A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.

Single-precision, floating-point register array for floating-point units

A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction. In response to a determination that the second instruction need not be completed prior to successfully dispatching subsequent instructions, execution of the floating-point store instruction is initiated by computing the destination address within memory into which the operand of the floating-point store instruction is to be stored, thereby minimizing the delay in executing a floating-point store instruction.

Processor and method for managing execution of an instruction which

A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit. If the speculative load instruction is executed in response to the control signals, then the associated bit in the enable speculative load table will be set to the first state. However, if the speculative load instruction is not executed in response to the control signals, then the associated bit in the enable speculative load table is set to the second state. In this manner, the displacement of useful data in the data cache due to wrongful execution of the speculative load instruction is avoided.

Method for executing speculative load instructions in high-performance

An arithmetic unit rapidly performs an XY+B floating point operation and yields a result equivalent to truncation of the product of X and Y before adding to B. Standard circuitry produces partial products from multiplier X and multiplicand Y, and a standard adder adds the partial products to yield a sum vector and a carry vector. Meanwhile, other circuitry predicts whether a most significant digit of a sum of the sum vector and the carry vector is zero or nonzero, based on less than all bits of the multiplier X and the multiplicand Y. If the most significant digit is certainly not equal to zero, a multiplexing circuit passes to a second adder a most significant N digits of the sum vector, a most significant N digits of the carry vector, a carry bit resulting from addition an (N-1)th most significant digit and lesser significant digits of the sum vector with an (N+1)th most significant digit and less significant digits of the carry vector, and an operand B. If the most significant digit is certainly equal to zero, then the multiplexing circuitry passes to the second adder a most significant N+1 digits of the sum vector, a most significant N+1 digits of the carry vector, a carry bit resulting from the addition of an (N+2)th most significant digit and less significant digits of the sum vector with an (N+2)th most significant digit and lesser significant digits of the carry vector, and the operand B.

Arithmetic unit for performing XY+B operation

The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

Growing community of inventors

Austin, TX, United States of America

Michael Putrino