3dlabs Inc., Ltd.

Avocent Corporation

Intergraph Corporation

Michael Potter

Clifford A Whitmore

Jeff S Ford

William Lazenby

Gary William Shelton

James Leroy Deming

A video compression system compresses video frames comprising pixels defined by n-bit color values. Encoder of video compression system determines the difference between a current pixel value and a plurality reference pixel values. Encoder sends difference value to decoder. Decoder determines current pixel value by adjusting a reference pixel color value by delta value.

DVC delta commands

An apparatus for processing data includes a first processor and a second processor. The first processor receives a source clock signal and converts the source clock signal to a first timing signal with a first phase. The second processor receives the source clock signal and converts the source clock signal to a second timing signal with a second phase. A phase connection circuit coupled to the first processor and the second processor determines whether the first phase is equivalent to the second phase. If the first phase and the second phase are not equivalent, the first processor will modify the first phase such that the first phase and the second phase are equivalent. The first processor may modify the first phase by inverting the first timing signal or by adding a clock delay to the first timing signal.

Phase correction for multiple processors

An apparatus for processing a graphical data stream for display on a display device includes a processor, a first conversion module and a second conversion module. The processor determines the characteristics of the graphical data stream. The first conversion module and the second conversion module convert the graphical data stream in a first format to a second format. The graphical data stream is directed to the first conversion module by a first data path and the graphical data stream is directed to the second conversion module by a second data path. A switching system is used to alternately connect the first conversion module through the first data path and the second conversion module through the second data path.

Apparatus for providing videodriving capability from various types of DACS

A back end unit for use with a graphics processor includes an input for receiving graphics data streams from the graphics processor, an output for transmitting graphics data streams, and a plurality of paths, coupled with the input and output, that direct graphics data streams between the input and the output. The plurality of paths direct data between the various modules that are a part of the back end unit. To that end, among other things, the back end unit also includes a gamma correction module that applies gamma correction operations to graphics data streams, a cursor module that adds cursor data to graphics data streams, and a digital to analog converter that converts the graphics data streams from a digital format to an analog format. The plurality of paths thus permit graphics data streams to pass through no more than two of the gamma correction module, the cursor module, and the digital to analog converter.

Selectable back end unit

An apparatus and method for displaying a television signal on a computer monitor first receives a selected first field data block of the television signal for display by the monitor. The television signal preferably includes a stream of first field data blocks and second field data blocks that are intended for display by respective first and second sets of lines on the computer monitor. After receipt of the first field data block, an immediately preceding second field data block is faded to produce a faded second block. The faded second block then is displayed on the second set of lines of the monitor, and the first field data block is displayed on the first set of lines of the monitor.

System for displaying a television signal on a computer monitor

An apparatus for and method of directing graphical data toward a display device from a plurality of graphics processors couples the graphics processors in a manner that reduces the size of the interface on each graphics processor. In particular, each graphics processor produces graphical data for an associated set of pixels on the display device, where each pixel is represented by a first amount of graphical data. The graphics processors are arranged so that one of the graphics processors is a destination processor. The total number of graphics processors that are not designated as the destination processor thus constitute a remaining number. Each graphics processor produces a second amount of graphical data during each clock cycle of a common clock. The first amount of graphical data, however, is comprised of at least substantially two times the second amount of graphical data. The graphics processors then are coupled so that during each clock cycle, the destination processor receives no more graphical data from the other processors than an amount equal to the product of the remaining number and the second amount.

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Huntsville, AL, United States of America

Michael Potter