Acuity Imaging, LLC

Robotic Vision Systems, Inc.

Microscan Systems Incorporated

Michael Philip Greenberg

Michael J Wilt

David C Davies

John E Agapakis

Thomas J Driscoll

Cynthia Berend

Embodiments of a dust-proof and water-proof enclosure for a camera. The enclosure includes first and second housings joined along a diagonal plane with a sealing element positioned on the diagonal plane between the two housings. An optical assembly is secured to at least one optoelectronic housing, and the optoelectronic housing is secured to a sidewall of the first housing. At least one electrical connector is secured to the sidewall of the second housing that is opposite the sidewall of the first housing to which the optoelectronic housing is secured when the first and second housing are joined.

Camera enclosure sealing system and method

A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.

Flexible processing hardware architecture

A power control system and method controls power supplied from a power source to a resistive load, such as a LED illumination array, to prevent the load from exceeding a high temperature limit. The power control system and method generates a pulse train that represents heating in the load and uses digital logic to model the load temperature and calculate a temperature out value. When the temperature out value increases to reach a high temperature limit value, the power source is disconnected from the load. When the temperature out value decreases to reach a base temperature value, the power source is re-connected to the load.

Power control system and method for illumination array

A power control system, which serves to protect a dissipative/resistive load from exceeding a predetermined temperature limit. The power control system accurately models the temperature of the load and enforces a cooling period to reduce the temperature of the load being protected to a base temperature level if the predetermined temperature limit is reached. Also provided is a method of selectively connecting and disconnecting a resistive load to and from a power source to prevent the resistive load from exceeding a predetermined high temperature limit. The method includes sensing a voltage proportional to the instantaneous power passing through the resistive load by wiring a current sensing resistor in series with the resistive load. Then, a load temperature is modeled using a load temperature modeling circuit to produce an output voltage proportional to a present temperature of the resistive load. A power switch is then selectively controlled to disconnect said power source from the resistive load when a high temperature limit is reached and to re-connect the power source to the resistive load when a base temperature is reached.

Power control system for illumination array

A data processing system including a data processor, also called a processing accelerator, processes at least one processor word each clock cycle. Each processor word includes multiple complete data samples which are received individually as part of a sequential stream of logically adjacent or related data samples such as in image data pixels which are part of an image to be processed by a machine vision system. A predetermined number of the data samples are stored together, as a processor word, in dedicated processing accelerator memory. For example, four 8 bit data samples can be stored together as one 32 bit processor word. The system also includes a data aligner which allows the processing accelerator to process at least one processor word comprised of at least one data sample from two processor words. The aligner controls data sample alignment such as for example, pixel alignment in the case of a vision system, to facilitate image data processing. Various processing units are also disclosed including: a neighborhood formation processing unit which, in a vision system, allows the processing accelerator to evaluate and process data within a neighborhood of one or more particular data elements, such as a pixel.

Data processing system for logically adjacent data samples such as image data in a machine vision system

A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data. The resampler further includes an interpolation unit, which receives pixel data from the second FIFO memory unit and interpolation fractions from the first FIFO memory unit. The interpolation unit then computes rendered result pixels, assembles the result pixels into memory words and outputs the words to a destination memory address, which is supplied by an address generator in a destination memory subsystem via a third FIFO memory unit.

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Goffstown, NH, United States of America

Michael Philip Greenberg