Enhanced Memory Systems, Inc.

Michael Peters

Kenneth J Mobley

David W Bondurant

David Fisch

Bruce Grieshaber

Michael Alwais

A double data rate (&ldquo;DDR&rdquo;) synchronous dynamic random access memory (&ldquo;SDRAM&rdquo;) device incorporating a static random access memory (&ldquo;SRAM&rdquo;) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page &ldquo;hit&rdquo; latency, faster page &ldquo;miss&rdquo; latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read &ldquo;hit&rdquo;.

Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank

An enhanced bus turnaround integrated circuit dynamic random access memory (&ldquo;DRAM&rdquo;) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (&ldquo;ZBT&rdquo;), or pipeline burst static random access memory (&ldquo;SRAM&rdquo;) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a &ldquo;Wait&rdquo; pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

Enhanced bus turnaround integrated circuit dynamic random access memory device

A multi-bank ESDRAM, and an associated method, provides for the caching of data accessed from any DRAM memory array of the multi-bank ESDRAM device to any SRAM cache register of the ESDRAM device. Execution of a read operation is carried out using an existing command set utilized to read data from conventional ESDRAM devices.

Multi-bank ESDRAM with cross-coupled SRAM cache registers

An enhanced bus turnaround integrated circuit dynamic random access memory ('DRAM') device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ('ZBT'), or pipeline burst static random access memory ('SRAM') devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a 'Wait' pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

Enhanced bus turnaround integrated circuit dynamic random access memory

An integrated circuit device, and an associated method, in which a logic element, such as a central processing unit, is embedded together with an EDRAM EDRAM (Enhanced Dynamic Random Access Memory) upon a common substrate die. A memory bus interconnects the EDRAM and the logic element. Data thruput rates of memory read and write operations are permitted to be of increased rates relative to the rates permitted of conventional, discrete devices.

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Colorado Springs, CO, United States of America

Michael Peters