Atheros Communications, Inc.

Qualcomm Incorporated

Level One Communications, Inc.

Qualcomm Atheros Inc.

Other

Intel Corporation

Michael Peter Mack

Paul J Husted

Srenik Suresh Mehta

Yann Ly-Gagnon

Manolis Terrovitis

Sang-Min Lee

Soner Ozgur

Shahriar Rabii

Brian James Kaczynski

MeeLan Lee

Christopher Donald Nilson

Hyunsik Park

Thomas Byunghak Cho

Sotirios Limotyrakis

Menno Marringa

Donald Evan Macnally

Laurence Marguerite Plouvier

Eric S Dukatz

This disclosure is directed to a wireless device with a suppressor that couples to the aggressor signal of a frequency source to generate a cancelling signal for suppressing spurs resulting from operation of the frequency source. The amplitude and phase delay of the cancelling signal are adjusted to optimize the cancellation of the spur. Preferably, a calibration routine is performed to establish appropriate delay and amplitude values to cancel the spurs occurring at each device gain setting.

System and method for RF spur cancellation

A mechanism can be implemented in a communication unit of a network device to utilize periods of silence encountered in voice communication to conserve power at the network device. In some embodiments, it can be determined that one or more packets of a received RF signal comprise audio data. The communication unit of the network device can determine whether the audio data associated with the one or more packets comprises voice information. The network device can switch to a power save mode based, at least in part, on determining that the audio data associated with the one or more packets does not comprise voice information.

Voice activity detection in communication devices for power saving

A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.

Tri-state control for a line driver

A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

Hybrid successive approximation analog-to-digital converter

A device and method for adjusting transmit power in a wireless communication device. The wireless communication device comprises a transmitter having a power amplifier, wherein the amplifier may introduce distortion into the transmit signal. The method may periodically determine an error vector magnitude (EVM) level in the transmitter of the wireless communication device. The EVM level may be determined based on differences between an ideal transmit signal without amplification, and an actual transmit signal with amplification. The method may then adjust one or more transmit gain settings of at least one gain stage of the wireless device based on the measured EVM level in the transmitter. In one embodiment, as the EVM increases, indicating that more distortion is being introduced, the method may reduce the gain settings of the gain stage(s) to reduce this distortion. If the EVM decreases, the method may increase the gain of the gain stage(s).

Transmit power control utilizing loopback error vector magnitude thresholds

A method and apparatus for configuring an oscillator circuit to selectively switch between a low power mode and a normal mode of operation. The oscillator circuit includes an oscillator core in parallel with a dynamically configurable gain circuit. The oscillator core is configured to generate a clock signal. One or more gain elements of the gain circuit can be selectively disabled to reduce the operating power level of the oscillator circuit during a low power mode.

Oscillators with low power mode of operation

A system and/or integrated circuit are disclosed that may include a receiver, a harmonic signal generator and a signal injector. The receiver may use at least one signal line to create a baseband signal to further create a quality measure used to improve the quality of reception and based upon the receiver response to the baseband signal. The harmonic signal generator may generate harmonic signal(s) including at least one harmonic component within the receiver's reception range. The signal injector may receive the harmonic signal and a control signal to generate the signal line from the harmonic signal in response to the control signal. The receiver may implement WLAN, Bluetooth, GPS, AM, mobile TV, FM, and/or Television. A transmitter compatible with the receiver may or may not be included, and may be configured to couple at least one of its outputs to the receiver to create a second quality measure.

Standalone testing of a receiver

A low drop out voltage regulator (LDO) is capable of operating in one of two different modes based on externally connected components. In one mode, the LDO directly generates a regulated output voltage. In a second mode, the LDO drives an external PNP transistor to generate a regulated output voltage. In both modes, a relatively large bypass capacitor may be connected to the output voltage node to bypass high-frequency loading on the output voltage node. However, the bypass capacitor creates a low frequency pole in the frequency response of the LDO, which can diminish phase margin and reduce overall stability. An on chip compensation network beneficially counteracts the low frequency pole with an appropriately placed zero, thereby resulting in improved phase margin and greater stability.

Configurable low drop out regulator circuit

A method of generating a quadrature local oscillator (LO) frequencies is provided. In this method, a voltage-controlled oscillator (VCO) frequency can be mixed with a divided version of the VCO frequency to generate mixed signals. A lower sideband of the mixed signals can be selected for the quadrature LO frequencies to minimize the occurrence of spurs. Notably, the divided version is 1/N of the VCO frequency and the VCO frequency is a radio frequency (RF) channel frequency times a ratio N/(N&#x2212;1).

Quadrature local oscillator generation for direct conversion radio transceiver

A method of providing current mode pulse frequency modulation (PFM) for a switching regulator can include resetting a driver input for a fixed duration when a first current in the driver reaches a first value set by an error amplifier output. The first current can be associated with PMOS switching transistors in the driver. The method can also include setting the driver input signal for the same fixed duration when a second current in the driver reaches a second value. This second current can be associated with NMOS switching transistors in the driver. In one embodiment, the driver can be tristated to ignore both the resetting and the setting. Using this method, perturbations of the inductor current can be substantially corrected and have limited impact on the current waveform beyond the cycle in which they occur.

Current mode pulse frequency modulation switching regulator

A compact constant current generator that can operate with a positive supply voltage of 1.22 V (or lower) and minimize noise is provided. The constant current generator can include a bandgap reference circuit and a single gain stage. Notably, the bandgap reference circuit can advantageously generate differential node voltages. The gain stage can amplify those differential node voltages and generate a constant current having a temperature coefficient substantially equal to zero. Advantageously, this single gain stage can minimize the number of components, thereby resulting in a compact and efficient current generator.

Constant current and voltage generator

Using separate synthesizers in a radio frequency (RF) device can facilitate avoiding interference. Specifically, a first synthesizer can be programmed to generate a first output frequency signal having an Frf frequency. A second synthesizer can be programmed to generate a second output frequency signal having an Fif frequency. Notably, a sum of the Frf and Fif frequencies equals an Fchannel frequency of the RF device. Thus, any RF channel can be received (or transmitted) with a plurality of VCO frequencies for each of the two synthesizers. A table of Frf/Fif combinations can be used to determine an Frf/Fif combination that avoids a known interfering source. Alternatively, Frf/Fif combinations can be randomly chosen until an interfering source is avoided.

Dual synthesizer RF frequency plan optimized for interference avoidance

A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.

Commutating phase selector

A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.

Growing community of inventors

Sunnyvale, CA, United States of America

Michael Peter Mack