Proton World International N.v.

Stmicroelectronics (Rousset) Sas

Telit Automotive Solutions Nv

Stmicroelectronics Belgium

Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Titan Automotive Solutions Nv

Stmicroelectronics (Grenoble 2) Sas

Michael Peeters

Jean-Louis Modave

Fabrice Marinet

Tim Froidcoeur

Stephen D Panshin

Fabrice Romain

Claude Debast

Ronny Van Keer

Bruno Motte

Joan Daemen

Guillaume Docquier

Francesco Caserta

Michel Dawirs

Thierry Simon

Kyle L Michel

Jefferson P Ward

An electronic device includes processing circuitry and one or more memories, including a non-volatile memory. Ephemeral cryptographic key generation circuitry, in operation, applies a function to code stored in the non-volatile memory, generating an ephemeral cryptographic key. Cryptographic circuitry coupled between the processing circuitry and the one or more memories, in operation, performs one or more cryptographic operations on data using the generated ephemeral cryptographic key. The device may include a register, which, in operation, temporarily stores the generated ephemeral cryptographic key.

Encryption and/or decryption key device, system and method

The present disclosure relates to authenticating a first device to a second device, including at least two successive verification operations comprising the following successive steps. The second device generates a first data, and sends the first data to the first device. The first device generates a third data and a fourth data used by the following verification operation and sends the third data to the second device. The second device checks the third data indicating whether the check was successful or not.

Authentication method and device

An authentication method is used in pairing a peripheral device to a companion device. The peripheral device sends a first identifier and a first value of a first counter to the companion device. The companion device verifies whether a pairing table stored in the companion device contains the first identifier. When the pairing table does not include the first identifier the companion device initiates a pairing session. When the pairing table includes the first identifier, the companion device compares the first value to a second value associated with the first identifier in the pairing table. In response to the first value being greater than the second value, the companion devices initiates a nominal session and in response to the first value being lower than or equal to the second value, execution of the method is stopped.

Method of performing an authentication method and a pairing of a peripheral device to a companion device

The present disclosure relates to an authentication method of a first device by a second device, each first, second device having a processor, at least one memory, and an authentication circuit, in which the authentication circuit is configured to prohibit the processor from reading data stored in at least part of said memory. The authenticating includes generating a first datum, and a second datum. The second device verifies that the first and second data match.

Authentication device, method and system

The present disclosure relates to secure storage, in a non-volatile memory, of initial data encrypted using a second data, including selecting a pointer aimed at an initial address of a memory cell of an initial part of the non-volatile memory, and encrypting the pointer using the second data; and-storing the encrypted pointer in the non-volatile memory.

Memory storage device and method

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

Processor authentication method

Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to: wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.

Keys for elliptic curve cryptography

The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased.

Monotonic counter

A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N&#x2212;3.

The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.

A first circuit is authenticated using a second circuit. A first datum and a second datum are stored in the second circuit. The second datum corresponds to an application of a first function to the first datum and a third datum. The second circuit sends the second datum to the first circuit. The first circuit decrypts the second datum and sends a fourth datum representative of a result of the decrypting to the first second circuit for authentication. The second circuit verifies a correspondence between the first datum and the fourth datum.

Authentication method

Processor authentication method through signed instruction

A volatile memory circuit includes a first flip-flop, a second flip-flop having a set input coupled to an output of the first flip-flop. Logic circuitry of the memory circuit logically combines an output of the second flip-flop and information representative of the output of the first flip-flop to generate an output of the memory circuit. In response to a read command, the first flip-flop is reset and content of the second flip-flop is output by the circuit.

Read-once memory

A memory includes a rewritable non-volatile memory cell and input circuitry coupled to the memory cell. The input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell. Similarly, a read-once memory includes an addressable, non-volatile memory having a plurality of rewriteable memory cells. Input circuitry coupled to the non-volatile memory responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory.

Growing community of inventors

Tourinnes-la-Grosse, Belgium

Michael Peeters