Teradata Us, Inc.

Intel Corporation

Mcdata Corporation

Idea Corporation

Sanera Systems, Inc.

Michael Paul Corwin

Joseph I Chamdani

Jeremy L Branscome

Liuxi Yang

Tse-Yu Yeh

Harshvardhan P Sharangpani

Krishnan Meiyyappan

Dale Calvin Morris

Kapil Laxmikant Surlaker

Ravi Krishnamurthy

Mircea Poplingher

James Shau

Sujat Jamil

Hans J Mulder

Kent G Fielden

Ken Arora

Millind Mittal

Michael S Schlansker

Rajiv Gupta

David T Hass

Nhon Toai Quach

Sailesh Kottapalli

Rajasekhar Cherabuddi

Judge K Arora

Wenliang Chen

Luke E Girard

Sunny C Huang

Hung Viet Tran

Stuart E Sailer

Stephen Trevitt

Carl C Scafidi

Jeen Miin

Robert Steven Gottlieb

Syed Reza

Alan Lee Beck

Raj Cherabuddi

Matthew S Rogge

Robert Hou

Liuxi Lang

James Hull

Ravindran Krishnamurthy

Norm Wayne Smith

Huang Kuang Hu

Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system.

Methods and systems for hardware acceleration of database operations and queries for a versioned database based on multiple hardware accelerators

Embodiments of the present invention provide hardware-friendly indexing of databases. In particular, forward and reverse indexing are utilized to allow for easy traversal of primary key to foreign key relationships. A novel structure known as a hit list also allows for easy scanning of various indexes in hardware. Group indexing is provided for flexible support of complex group key definition, such as for date range indexing and text indexing. A Replicated Reordered Column (RRC) may also be added to the group index to convert random I/O pattern into sequential I/O of only needed column elements.

Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns

Embodiments of the present invention provide one or more hardware-friendly data structures that enable efficient hardware acceleration of database operations. In particular, the present invention employs a column-store format for the database. In the database, column-groups are stored with implicit row ids (RIDs) and a RID-to-primary key column having both column-store and row-store benefits via column hopping and a heap structure for adding new data. Fixed-width column compression allow for easy hardware database processing directly on the compressed data. A global database virtual address space is utilized that allows for arithmetic derivation of any physical address of the data regardless of its location. A word compression dictionary with token compare and sort index is also provided to allow for efficient hardware-based searching of text. A tuple reconstruction process is provided as well that allows hardware to reconstruct a row by stitching together data from multiple column groups.

Accessing data in column store database based on hardware compatible data structures

A memory channel can be divided into two or more memory sub-channels, wherein each one of the memory sub-channels includes two or more memory components configured to store data made accessible on that memory sub-channel, and wherein the two or more memory components in each one of the memory sub-channels are respectively connected via at least one transmission line and can be individually accessed (addressed) on their associated sub-channel.

Designated memory sub-channels for computing systems and environments

Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators

Embodiments of the present invention provide a database system that is optimized by using hardware acceleration. The system may be implemented in several variations to accommodate a wide range of queries and database sizes. In some embodiments, the system may comprise a host system that is coupled to one or more hardware accelerator components. The host system may execute software or provide an interface for receiving queries. The host system analyzes and parses these queries into tasks. The host system may then select some of the tasks and translate them into machine code instructions, which are executed by one or more hardware accelerator components. The tasks executed by hardware accelerators are generally those tasks that may be repetitive or processing intensive. Such tasks may include, for example, indexing, searching, sorting, table scanning, record filtering, and the like.

Methods and systems for hardware acceleration of database operations and queries

Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCle or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

Hardware accelerated reconfigurable processor for accelerating database operations and queries

Accessing data in a column store database based on hardware compatible data structures

A scalable solution to managing congestion in a network is disclosed. In one implementation, such a solution comprises a means for managing traffic including at least one flow monitor and a plurality of flow control regulators that together manage congestion within a network. Each of the flow control regulators monitor traffic at a corresponding ingress point and determine a state of the ingress point corresponding to the traffic monitored at the ingress point. Each flow control regulators forward the state (or information representative of the state) to the flow monitor. The flow monitor detects congestion based upon the states of the flow control regulators and, in the event of congestion, determines a target bandwidth for the ingress points. The flow monitor provides a control signal to at least one of the flow control regulators, and at least one of the flow control regulators control flows at its corresponding ingress point based upon the control signal received from the flow monitor.

Congestion management groups

Embodiments of the present invention provide a hardware accelerator that assists a host database system in processing its queries. The hardware accelerator comprises special purpose processing elements that are capable of receiving database query/operation tasks in the form of machine code database instructions, execute them in hardware without software, and return the query/operation result back to the host system. For example, table and column descriptors are embedded in the machine code database instructions. For ease of installation, the hardware accelerators employ a standard interconnect, such as a PCIe or HT interconnect. The processing elements implement a novel dataflow design and Inter Macro-Op Communication (IMC) data structures to execute the machine code database instructions. The hardware accelerator may also comprise a relatively large memory to enhance the hardware execution of the query/operation tasks requested. The hardware accelerator utilizes hardware-friendly memory addressing, which allows for arithmetic derivation of a physical address from a global database virtual address simply based on a row identifier. The hardware accelerator minimizes memory reads/writes by keeping most intermediate results flowing through IMCs in pipelined and parallel fashion. Furthermore, the hardware accelerator may employ task pipelining and pre-fetch pipelining to enhance its performance.

A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.

Multi-level content addressable memory

A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.

Packet switching apparatus including cascade ports and method for switching packets

Growing community of inventors

Sunnyvale, CA, United States of America

Michael Paul Corwin