International Business Machines Corporation

Michael Patrick Vachon

Agnes Yee Ngai

Charles E Boice

John Mark Kaczmarczyk

Robert L Woodard

Charlene Ann Gebler

Barbara A Hall

Louis Christopher Milano

Eric Eugene Retter

Dennis E Franklin

John A Murdock

Roger Sherman Rutter

Stanley J Kolodziejski

Richard W Furney

Anthony L Simenkiewicz

Gordon C Hurlbut

Two encoders are used in cascade wherein one encoder functions as a preprocessor for the other by collecting statistics concerning partially processed input data. The statistics thus derived are autonomously transferred to a second decoder in a self-synchronized manner, avoiding any need for external glue logic, and utilized to select encoding options for encoding and/or compressing the data so that the quality of encoded data is optimized based on the content of current input data.

Apparatus for integrated cascade encoding

An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.

Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency

An apparatus and method for extracting vertical (V-SYNC) and horizontal (H-Blank) sync signals from a digital composite sync signal (C-SYNC) of a master video source for use in controlling a second video source, which allows for an adjustable delay relationship between the C-SYNC from the master source and the generated H-Blank. The present invention also provides a system and method for varying the responsiveness or gain of the genlocking circuit used to synchronize the system pixel clock frequency of the second video source to that of the master video signal.

Highly adjustable video composite sync separator and variable gain pixel clock frequency locking apparatus and method

A digital video encode system, method and computer program product are described wherein a picture is divided into multiple active areas that are parallel encoded using multiple encoders. The encoders associated with adjoining active areas of the picture are configured to exchange reference data to facilitate avoiding appearance of a seam between the adjoining active areas of a subsequent picture in a sequence of pictures due to separate encoding thereof by the multiple encoders. The reference data transferred from one encoder to an adjoining encoder is an encoded and decoded section of the picture and is used by the adjoining encoder as an expanded reference area for motion estimation when encoding the subsequent picture.

Sharing reference data between multiple encoders parallel encoding a sequence of video frames

System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted. There are a variety of video input conditions that may be detected which will enable generation of a trigger signal indicating idle processing for one or more functional sub-units, including, for example, detection of still input pictures, fade sequences and specification of high bitstream output rates.

Apparatus and method for power reduction control in a video encoder device

Method and apparatus for detecting and correcting error in an uncompressed digital video image data stream. The method and apparatus identify error or partial picture scenarios. Each of the possible error or partial picture scenarios is identified in a Partial Picture Repair Unit, which causes error processing of the uncompressed video input stream, resulting in the creation of a repaired data stream on the repaired pixel bus. The repair begins upon detection of an erroneous picture, field, or line. Processing for that picture, field or line is stopped upon detection of an error in the synchronization signals, and processing is resumed when the end of line, end of field, or end of picture indicator is detected.

Method and apparatus to accommodate partial picture input to an MPEG-compliant encoder

A filter for downsampling input video having a first chrominance sampling to a second chrominance sampling. The input video has a Bitstream of data representing a sequence of picture frames, where each picture frame has a plurality of video lines. The filter has a means for choosing a downsampling mode from a list of available downsampling modes for the downsampling of the first chrominance sampling. The filter also has a means for dividing each picture frame into video line sets according to predetermined criteria for the particular downsampling mode chosen, where each video line set has at least two video lines. A means for assigning default downsampling coefficients for each of the video lines in the video line sets based upon the downsampling mode chosen is also provided in the filter. Lastly, the filter has a means for downsampling each video line set to a single video line having the second chrominance sampling. In a preferred embodiment, the first chrominance sampling is 4:2:2 and the second chrominance sampling is 4:2:0.

Highly programmable chrominance filter for 4:2:2 to 4:2:0 conversion during MPEG2 video encoding

More than 2 power N external conditions are determined by a circuit package. Connections are made from N inputs to either a first or second contact at either a first or second logic state respectively or to digital outputs. The outputs may be sequentially placed at either the first or second logic state. By recording an indication signal from the inputs an electronic circuit is adapted to determine more than 2 power N conditions.

Circuit and method for differentiating multiple modules

A method to compensate for a fade in a digital video input sequence is provided where the video input sequence is to be compressed according to the MPEG-2 video compression standard. The method comprises a first step of dividing each frame of a current frame into two fields. In a second step, each field of the current frame is divided into at least one field band. In a third step, the luminance and chrominance pixel values are individually summed for the pixels in each field of the current frame. In a fourth step, the luminance pixel values are summed for the pixels in each field band of the current frame. In a fifth step, each respective field band sum and field sum of the current frame is compared with that of the previous frame in the video input sequence. In a sixth step, detection of whether or not a fade has occurred is provided, based upon the comparison in the fifth step. In a seventh step, the encoding algorithm is adjusted if a fade has occurred. Lastly, the first through seventh steps are repeated for at least one subsequent frame in the input video sequence.

Method to compensate for a fade in a digital video input sequence

Method and apparatus to accommodate partial picture input to an

Disclosed is an integrated microprocessor chip. The chip includes a digital video decoder Inverse Discrete Cosine Transform element and an on chip Read Only Memory. The on chip Read Only Memory includes (a) a shift register latch for receiving data from off chip pull-up resistors, (b) a register for storing data, (c) a selector and a decoder for selecting memory cells to be read from the register, and (d) a Read Only Memory data output.

Integrated circuit including fully testable small scale read only memory

A cache storage system is disclosed which has a high speed buffer (cache), a directory-look-aside-table, and apparatus for maintaining binary coded information signifying the order of use of various sections of the cache. A separately addressable and controllable storage array is provided for each bit position of the binary code so that updating of a code is accomplished by selectively writing certain but not all of the bits in the arrays storing said bits to be updated. This avoids the need to read all bits from an array, change the appropriate bits, then write all bits back into the array. Bits signifying the changed or unchanged state of data in said various sections of the cache are also stored in separately addressable arrays to permit updating of their value merely by selectively writing to the appropriate array.

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Johnson City, NY, United States of America

Michael Patrick Vachon