International Business Machines Corporation

Globalfoundries Inc.

Applied Materials, Inc.

Other

Advanced Micro Devices Corporation

Infineon Technologies Ag

University of Chicago

Globalfoundries U.S. 2 LLC

Advanced Micro Device, Inc.

Michael Patrick Chudzik

Siddarth A Krishnan

Vijay Narayanan

Unoh Kwon

Joseph Francis Shepard, Jr

Vamsi Krishna Paruchuri

Shahab Siddiqui

William K Henson

Keith Kwong Hon Wong

Rishikesh Krishnan

Rajarao Jammy

Renee Tong Mo

Takashi Ando

Carl John Radens

Dae-Gyu Park

Bruce Bennett Doris

Barry P Linder

Oleg Gluschenkov

Martin Michael Frank

Jinping Liu

Alessandro Cesare Callegari

Naomi Yoshida

Judson Robert Holt

Dominic Joseph Schepis

Ravikumar Ramachandran

Huiming Bu

Benjamin Colombeau

Jeffrey P Gambino

Ramachandra Divakaruni

Supratik Guha

Herbert Lei Ho

Shreesh Narasimha

Andrew Herbert Simon

Zhengwen O Li

Eduard Albert Cartier

Brian Joseph Greene

Errol Antonio C Sanchez

Stephen W Bedell

Louis L Hsu

Jeffrey W Sleight

Dechao Guo

James William Adkisson

Kern Rim

Richard Stephan Wise

Helmut Horst Tews

Kangguo Cheng

Edward J Nowak

Lawrence Alfred Clevenger

Jack Allan Mandelman

Toshiharu Furukawa

Yun Yu Wang

Shu-Jen Han

Ying Di Zhang

Sampath Purushothaman

Christian Lavoie

Chengwen Pei

Robert H Dennard

Tze-Chiang Chen

Deborah A Neumayer

Chandrasekhar Narayan

Anna Wanda Topol

Jochen C Beintner

Wesley Charles Natzle

Matthew Warren Copel

Bruce Kenneth Furman

Paul Christian Parries

Rama Divakaruni

Lan Yu

Devendra K Sadana

Ghavam G Shahidi

William R Tonti

Haining S Yang

Josephine B Chang

Michael A Guillorn

Cyril Cabral, Jr

Geng Wang

Arvind Kumar

Zhen Zhang

Mark Joseph Saly

Damon B Farmer

Thomas W Dyer

Sufi Zafar

Seshadri Ganguli

Robert C Wong

Paul F Ma

Richard Alan Haight

Anthony I Chou

Henry K Utomo

Johnathan E Faltermeier

John Christopher Arnold

Roger Allan Quon

Byeong Yeol Kim

James N Pan

Bhaskar Jyoti Bhuyan

Kathryn Turner Schonenberg

Yanxiang Liu

Yixiong Yang

Werner A Rausch

Uthamalingam Balachandran

Joseph R Johnson

Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal.

Indium-gallium-nitride light emitting diodes with light reflecting mirrors

Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium-and-nitrogen-containing region.

Indium-gallium-nitride light emitting diodes with increased red-light quantum efficiency

Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.

Methods to fabricate dual pore devices

Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

Deep trench integration processes and devices

Exemplary devices may include a substrate, a dielectric layer formed on the substrate, a first light source configured to emit first light characterized by a first wavelength, a second light source configured to emit second light characterized by a second wavelength different from the first wavelength, and a third light source configured to emit third light characterized by a third wavelength different from the first wavelength and the second wavelength. The first light source may be natively formed on a first region of the substrate and arranged within a first opening of the dielectric layer. The second light source may be natively formed on a second region of the substrate and arranged within a second opening of the dielectric layer. The third light source may be natively formed on a third region of the substrate and arranged within a third opening of the dielectric layer.

Three color light sources integrated on a single wafer

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Horizontal gate all around and FinFET device isolation

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Horizontal gate all around device isolation

A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Trench metal insulator metal capacitor with oxygen gettering layer

A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Hydroxyl group termination for nucleation of a dielectric metallic oxide

Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

Fabrication of IC structure with metal plug

Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

Multi-threshold voltage structures with a lanthanum nitride film and methods of formation thereof

An aspect of the disclosure is directed to a method of forming an interconnect for use in an integrated circuit. The method comprises: forming an opening in a dielectric layer on a substrate; filling the opening with a metal such that an overburden outside of the opening is created; subjecting the metal to a microwave energy dose such that atoms from the overburden migrate to within the opening; and planarizing the metal to a top surface of the opening to remove the overburden, thereby forming the interconnect.

Integrated circuit having improved electromigration performance and method of forming same

A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

Fabrication of higher-K dielectrics

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Danbury, CT, United States of America

Michael Patrick Chudzik