International Business Machines Corporation

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Michael P Taborn

Steven Michael Burchfiel

Paul K Miller

David Terrence Matheny

Roger Ned Bailey

Larry R Metzger

Richard Jacob Wilcox

John K Yuan

Spencer A Peterson

David R Horton

A method and apparatus for capturing the internal state of an integrated circuit (IC) for second and higher order speedpath-induced failures. The method includes stretching one or more cycles of an internal clock signal in order to mask a first order speedpath-induced failure (SIF), wherein the internal clock signal is restored to operating at a normal speed subsequent to masking the first order SIF. The internal clock signal may be stopped at a cycle corresponding to a higher order SIF. After stopping the internal clock signal, test output data may be loaded into a scan chain. The method may also be used in conjunction with a laser or other device for other test enhancements.

Method and apparatus for capturing the internal state of a processor for second and higher order speepaths

A floating point processing system and method of operation are disclosed. Single word precision denormalized operands and also misaligned operands are detected while such operands are being loaded into the first stage of a pipelined floating point unit. Such operands are aligned to a double word boundary and/or single word operands are normalized by a processing stages inserted into the pipe ahead of the first stage of the pipelined floating point unit thereby entering a one stage delay. In this way, misaligned operands and single word denormalized operands can be processed without the need for example to cancel the instruction, execute a normalize or alignment instruction and then re-launch the original instruction.

Variable stage load path and method of operation

A system and method for denormalizing a floating point result is disclosed. Denormalized operands are capable of representing much smaller values than can be represented by a number normalized under the ANSI/IEEE standard 754-1985 that governs the representation of numbers in floating point notation to ensure uniformity among floating point notation users. The majority of results will be normalized operands and therefore the floating point unit pipeline is optimized to produce normalized results but contains wider exponent fields in order to represent values received as denormalized numbers. In order to return the result as a denormalized number with the smaller ANSI/IEEE exponent field, denormalization is accomplished by using the same pipeline resources by means of the floating point unit feedback path and uses one of the exponent equalizing alignment shifters and an incrementor in order to round the denormalized result. In this way, denormalized results can be provided without stopping the dispatching of instructions, without providing status bits in the register files and rename registers and without the hold signals often present in other floating point units to accomplish denormalization.

Denormalization system and method of operation

An underflow/overflow detector includes first circuitry that decodes an exponent into an exponent shift value and compares the exponent shift value with a normalize shift value to determine whether an underflow or overflow error will occur. The underflow overflow detector further includes second circuitry that compares the exponent to a maximum and minimum exponent value to determine whether an underflow or overflow error will occur.

Method and apparatus for detecting underflow and overflow

An apparatus for rounding an answer produced during the execution of an operation by a multiple stage execution pipeline includes first circuitry for detecting when the operation is iterative and accuracy bits associated with the answer to determine if a rounding calculation is required. When the first circuitry detects a rounding calculation is required, it sets a correction factor for the answer in accordance with a rounding mode and the detected accuracy. In a method practiced by the apparatus, the rounding an answer produced during the execution of an operation occurs through the steps of detecting, when the operation is iterative, accuracy bits associated with the answer to determine if a rounding calculation is required, and, when the rounding calculation is required, setting a correction factor for the answer in accordance with a rounding mode and the detected accuracy bits.

Method and apparatus for rounding the result of an arithmetic operation

A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a first transistor of the pair of cross-coupled transistors is connected to the output of a first precharge transistor that is powered by the upper rail and controlled by a clock. The output of a second transistor of the pair of cross-coupled transistors is connected to the output of a second precharge transistor that is powered by the upper rail and controlled by the clock. A logic circuit is wired to perform a logical function, either a Sum or a Carry function, and has a plurality of inputs, an output, and a complementary output. The output of the logic circuit is connected to the output of the first transistor of the pair of cross-coupled transistors, and the complementary output is connected to the output of the second transistor of the pair of cross-coupled transistors. An enable transistor having a first terminal connected to a lower voltage rail, and being controlled by the complement of the clock, has a second terminal connected to the logic circuit such that the logic circuit is connected to the lower voltage rail through the enable transistor.

Differential carry-save adder and multiplier

An apparatus for detecting sticky and a leading one includes first circuitry capable of detecting both sticky and a leading one. The apparatus further includes second circuitry that determines whether a sticky or a leading one detect is required. Depending upon that determination, the second circuitry controls the first circuitry to perform a sticky detection or a leading one detection. A method practiced by the apparatus includes the steps of detecting either sticky or a leading one utilizing the same circuitry, determining whether a sticky or a leading one detect is required, and controlling the circuitry in accordance with the determination of whether a sticky or a leading one detect is required.

Method and apparatus for sticky and leading one detection

A multi-featured first-in-first-out (FIFO) memory device on a monolithic semiconductor integrated circuit chip. The FIFO device is bi-directional, in that the user may select the direction of data transfer through the device. The device may be configured in a transparent bypass mode of operation, wherein the FIFO memory array is bypassed, and data is transferred directed from either device input/output port to the other device input/output port. In another mode of operation allowing registered bypass operation, a byte of data may be written in an internal register from the device port being used to output data for later transfer to the device port presently being used to input data to the FIFO memory array. The FIFO device further includes a user-testable mode of operation, wherein data written into the FIFO memory array through a device input port may be read out of the same device input port. Device mode selection occurs through control pin slew detection, allowing mode selection with a minimum number of control pins.

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Austin, TX, United States of America

Michael P Taborn