Compaq Computer Corporation, Inc.

Duke University

Hewlett-packard Development Company, L.P.

Compaq Information Technologies Group, L.p.

Michael P Moriarty

John Edward Larson

Gary W Thome

Thomas J Bonola

Michael J Collins

Thanh Thien Tran

Jens K Ramsey

Mark W Welker

Paul R Culley

Arnold Thomas Schnell

Mark E Taylor

Craig Walrath

Jeffrey C Stevens

Brian T Purcell

Roger E Tipley

Maria L Melo

Charles N Shaver

Jeff W Wolford

Giang H Dao

Michael P Medina

A digital television/local bus interface logic supports handling of digital television (DTV) data with non-tearing. The interface logic provides a dual frame buffer DTV architecture in which a pair of DTV/local bus frame buffers alternate functions: one frame buffer stores incoming DTV data and the other frame buffer stores the outgoing DTV data. When a refresh of a display device reaches a programmed position of the display device, the interface logic determines which frame buffer is being updated by the incoming DTV data. The outgoing DTV data is then read from an opposite frame buffer and transmitted to the display device. The interface logic receives a horizontal sync signal and a vertical sync signal from the graphics controller for monitoring refresh of the display device. The interface logic also provides an architecture for transferring decoded DTV data over a local bus to the graphics controller.

Method and apparatus for transmitting digital television data

In storing data for display, traditionally twenty-four bit video pixels have required extra video memory to store the video pixels on double word boundaries or extensive hardware to fully utilize video memory. Eight twenty-four bit video pixels are stored within three quad words in a manner that reduces the required hardware from prior approaches and fully utilizes video memory.

Efficient pixel packing

A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell. Ownership of the semaphore memory cell is thus achieved using a single operation by a busmaster. The properties of the self-modifying synchronization memory address space and the semaphore memory cell thus eliminate the need for assertion of a bus locking signal to achieve exclusive access for a busmaster to a shared critical resource. These properties also eliminate the need for host processor intervention in accessing a shared critical resource when a busmaster is a PCI master.

Self-modifying synchronization memory address space and protocol for communication between multiple busmasters of a computer system

A method and apparatus of allocating memory space in a main memory of a computer system to a unified memory architecture device. The main memory is associated with a physical address space. A required linear address range is determined for the video card, and the linear address range is mapped to scattered portions in the physical address space. A page table is created containing page frame numbers corresponding to page frames in the main memory, the page frames being allocated to the device. The page frames are non-contiguous blocks of the main memory. The device is associated with a linear address space. The frame numbers are loaded into a translation look-aside buffer (TLB) for converting a linear address in the linear address space to a physical address in the physical address space.

Method and system for allocating memory space using mapping controller, page table and frame numbers

A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.

Computer system controller and method with processor write posting hold off on PCI master memory request

A digital television (DTV) data format converter of a system automatically detects whether a serial data stream includes parity data and converts the serial DTV data stream to a parallel DTV data stream. The DTV data format converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a first conversion protocol if the serial DTV data stream includes parity data. If the serial DTV data stream does not include parity data, the converter transmits the parallel DTV data stream converted from the serial DTV data stream in accordance with a second conversion protocol. In this way, the converter accommodates a serial DTV data stream with or without parity data. The DTV data format converter may be implemented in the form of a peripheral component interconnect (PCI) card, permitting compatibility with computer systems and other PCI-based systems. The DTV data format converter may include a receiver block, a transmitter block, and a buffer.

Digital television data format conversion with automatic parity detection

An apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device, such as a bus bridge.

System having a bridge with distributed burst engine to decouple

A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.

Multimedia computer architecture with multi-channel concurrent memory

A multimedia system including a PCI bus master controller for transferring concurrent and independent video and audio data streams to video and audio devices. The controller includes a video request and DMA channel, a video sub-picture request and DMA channel, an audio request and DMA channel, and a decompressed video DMA and posted request channel for independently and concurrently transferring the data streams from host memory to the devices. The host processor builds lists of request packets in system memory and asynchronously submits the request packets to the controller. The request packets include commands which the request channels execute. The commands may include spinning on status conditions in registers of the multimedia devices, writing to registers of the devices, or performing bus master transfers of multimedia data streams from system memory to the devices. The device register accesses are performed by the controller on local buses thereby reducing PCI bus traffic.

System and method for transferring concurrent multi-media streams over a

A method and apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device.

Packet protocol and distributed burst engine

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.

Memory controller having precharge prediction based on processor and PCI

A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

Memory controller including write posting queues, bus read control

A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.

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Spring, TX, United States of America

Michael P Moriarty