Advanced Micro Devices Corporation

Michael P Duane

Mark I Gardner

Daniel Kadosh

Scott D Luning

David Donggang Wu

Robert Louis Dawson

Frederick N Hause

Jon D Cheek

Massud Aminpur

Derick J Wristers

Fred N Hause

Charles E May

Thomas E Spikes, Jr

Jeffrey C Haines

Brad T Moore

Steven E Bourland

A method is provided, the method including forming a gate dielectric above a surface of the substrate and forming a doped-poly gate structure above the gate dielectric, the doped-poly gate structure having an edge region. The method also includes forming a dopant-depleted-poly region in the cage region of the doped-poly gate structure adjacent the gate dielectric.

Semiconductor device and method for lowering miller capacitance for high-speed microprocessors

A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Channel isolation using dielectric isolation structures

A method is provided, the method including forming a gate dielectric above a surface of the substrate, forming the conductive gate structure above the gate dielectric, the conductive gate structure having an edge region, and forming a source/drain extension (SDE) adjacent the conductive gate structure. The method also includes forming a dopant-depleted-SDE region in the substrate under the edge region of the conductive gate structure.

Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors

A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

Elevated transistor fabrication technique

The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon and forming a recess in the layer of polysilicon. The method further comprises forming a metal region in the recess and patterning the layer of polysilicon to define a gate stack comprised of the metal region and the layer of polysilicon.

Method of forming low resistance gate electrode

An improved series-connected transistor architecture and a method for forming the same are provided. Gate conductors for series connected transistors are patterned such that gate conductors on either side of a merged source/drain region which will not be contacted in the completed circuit are spaced more closely together than other gate conductors. In an embodiment of the method, these closely-spaced gate conductors have a spacing between facing sidewalls of less than about twice the expected sidewall spacer width for the process. After a first dopant impurity introduction, a conformal dielectric layer is deposited and portions of the dielectric layer are removed to form sidewall spacers. In the region between the closely-spaced gate conductors, the spacers are merged to form a continuous dielectric. This dielectric protects the substrate between the closely-spaced gate conductors from subsequent impurity introduction and salicide processes. In an alternate embodiment, dielectrics are formed between and adjacent to all gate conductors using dielectric deposition and chemical-mechanical polishing. All dielectrics except those between the closely-spaced gate conductors are subsequently removed, and spacers are formed on exposed sidewalls of the gate conductors.

Merged sidewall spacer formed between series-connected MOSFETs for improved integrated circuit operation

An integrated circuit fabrication process is provided for forming, a mutual implant region within a well which is shared by a source region of a transistor residing within the well and a well-tie region coupled to the well, thereby providing a single electrical link to the well and the source region. Contacts may be coupled to the mutual implant region, and a conductor may be connected to the contacts. In the instance that the well is a p-type well in which NMOS transistors are formed, a ground voltage may be applied to the conductor to bias both the source region and the well. On the other hand, if the well is an n-type well in which PMOS transistors are formed, a power voltage, VCC, may be applied to the conductor to bias both the source region and the well. Absent the need to form contacts to both the source region and the well-tie region and conductors to such contacts, less space is required to bias the well and the source region. Also, merging a portion of the well-tie region with a portion of the source region affords increased packing density of an integrated circuit. The higher packing density is achieved without resorting to decreasing the dimensions of the well-tie region, and thus without detrimentally increasing the resistance of the well-tie region.

Mutual implant region used for applying power/ground to a source of a transistor and a well of a substrate

In a plurality of series-coupled IGFET devices, wherein each pair of devices in the series shares a common source/drain terminal, only the source/drain regions acting as drain terminals are provided with a lightly-doped region. The presence of the lightly-doped source/drain regions in the portions of the source/drain regions acting as drain terminals provides protection against &ldquo;hot-carrier&rdquo; effects. By not having lightly-doped portions in portions of the source/drain regions acting as sources, the resistance resulting from the presence of the additional lightly-doped portions of the remaining source/drain regions in the series of IGFET devices results in lower resistance experienced by the conduction current. According to a second embodiment of the invention, only the non-shared source/drain terminal acting as drain terminal is provided with a lightly-doped region. In this manner, a large portion of the &ldquo;hot-carrier&rdquo; effects are reduced, while the resistance to conduction current for the total resistance of the devices is lowered still further.

Mask for asymmetrical transistor formation with paired transistors

A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.

Method and structure for elevated source/drain with polished gate

A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.

Etch stop layer formed within a multi-layered gate conductor to provide

Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current--a desirable outcome for high speed circuits.

Asymmetrical transistor structure

A process for forming a semiconductor device having an elevated active region is disclosed. The process includes forming a plurality of gate electrodes on the semiconductor substrate and disposing a thick oxide layer over the gate electrodes. A trench is formed in a thick oxide layer and is filled with a polysilicon material. The polysilicon material is subsequently doped in order to form an elevated active region above an active region of the substrate.

Semiconductor device having an elevated active region formed in an oxide

A semiconductor device and process for manufacture thereof is disclosed in which a gate electrode with reduced overlap capacitance is formed by forming a gate electrode on a surface of a semiconductor and doping edge portions of the gate electrode with a first doping which effectively reduces the conductivity of the edge portions of the gate electrode. The conductivity of the gate electrode may be reduced at the edge portions by doping the edge portions with a dopant which inhibits the doping of the gate electrode or with a dopant which has a different conductivity type than the gate electrode dopant.

Semiconductor device having reduced overlap capacitance and method of

An IGFET device isolation structure fabrication scheme includes the formation of electrically insulating isolation structures that extend into the substrate and extend above the surface of the substrate. The isolation structures are formed by providing a first mask to form trenches in the substrate. A layer of silicon dioxide is then deposited, filling the trenches and extending above the surface of the substrate. A second mask layer is formed. The second mask layer shadows the trench regions that were formed in the substrate. The silicon dioxide not shadowed by the second mask layer is removed, leaving isolation structures that extend both into the substrate and which rise above the substrate. A gate structure is formed in the region between two isolation structures, and, in the preferred embodiment, the gate structure extends above the substrate to the same height as the isolation structures. The isolation structures and the gate structure can be used to provide self-aligned doped source/drain regions. Spacers can be added to the isolation structure walls and the gate structure walls to provide heavily-doped self-aligned regions.

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Austin, TX, United States of America

Michael P Duane