Analog Devices,inc.

Michael P Daly

Trey Roessig

Lawrence Howard Edelson

Kieran K Heffernan

David Thomson

A Paul Brokaw

David J Clarke

Jonathan Mark Audy

Denis Ellis

Evaldo M Miranda, Jr

Brian Anthony Moane

Michael G Tuthill

Denis J Doyle

Liam Joseph White

Christian Willibald Böhm

Christian Willibald B&ouml;hm

Keith A Moloney

An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a 'critical condition' in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.

Adaptive phase offset controller for multi-channel switching power converter

A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (I), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vat respective inputs, and a switchable current source connected to the input node which conducts a reference current Iwhen switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (V) at the input node when the comparator output toggles due to Vincreasing above V, and to be switched off when the comparator output toggles due to Vfalling below V, such that the comparator output comprises a digital bitstream which varies with I.

Sigma-delta conversion circuit suitable for photocurrent measurement applications

A serial digital communication system includes a master device and a plurality of slave devices connected serially between the master device's output and input&#x2014;thereby forming a closed chain. Each slave device transmits a predetermined number of PWM pulses to the device following it in the chain upon receipt of an end-of-transmission (EOT) signal from the device preceding it in the chain, and transmits an EOT signal when the transmission of its PWM pulses is completed. The master device transmits an EOT signal to initiate the transmission of PWM pulses from each slave device. Each slave device passively buffers PWM pulses received from the preceding device, such that PWM pulses are transmitted in one direction sequentially to the input of the master device via the intervening slave device.

Serial digital communication system and method

A communication system includes a master device which communicates with a chain of serially-connected slave devices. The master originates messages, each of which is intended for a particular 'target' slave device. Each message contains a 'distance to target device' value equal to the number of devices between the master and target, and a data packet containing data to be conveyed between the master and target. Each slave device determines if the &#x2018;distance to target device&#x2019; value indicates that it is the target. If not, the slave device increments or decrements the value in real time, with no latency, and transmits the modified message to the next slave device until received by the target device. In one embodiment, the target device may place data in the data packet, and the slave devices are arranged to buffer the data back to the master device.

A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

Synchronization pulse detection circuit

A voltage source includes first and second pn junctions which conduct the outputs of respective current sources to establish respective base-emitter voltages Vand Vat respective nodes; Vand Vcan each be generated with a current I or a current N*I. An amplifier Ahas its non-inverting input connected to the second node and its inverting input connected to the first node through an input capacitor; a feedback capacitor is connected between the inverting input and a third node. Switches are connected between A's inverting input and A's output, between the third node and A's output, and between the third node and a circuit common point. A control circuit operates the switches and current sources during first and second operating phases to selectively produce a temperature independent output voltage or a temperature dependent output voltage.

Voltage source circuit with selectable temperature independent and temperature dependent voltage outputs

A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has &ldquo;level&rdquo; portions (i.e., substantially non-time varying portions) and &ldquo;transition&rdquo; portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first &ldquo;level&rdquo; portion, followed by a first &ldquo;transition&rdquo; portion, followed by a second &ldquo;level&rdquo; portion, followed by a second &ldquo;transition&rdquo; portion followed by a third &ldquo;level&rdquo; portion, one of the first and second &ldquo;transition&rdquo; portions being positive and the other one of the first and second &ldquo;transition&rdquo; portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses. In one embodiment, the input signal is a video signal and the evaluator includes a time window for determining whether such shape_detected pulses are produced at a predetermined rate expected for the series of synchronization pulses. The evaluator includes a voltage window responsive to the produced shape_detected pulses and their associated values of the second &ldquo;level&rdquo; portions for determining whether one of such produced second &ldquo;level&rdquo; portions is substantially the same as or lower but not higher than the lowest DC value recorded during the time-equivalent of one line of video. The evaluator may include both the time window and the voltage window. The voltage window is mainly used to acquire an initial lock to an unknown and not yet clamped video signal.

An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node. In a second aspect to the invention, a further region of heavily doped P-type material is formed in the first lightly-doped region of P-type material. In a third aspect to the invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this third aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node, with a further region of heavily doped P-type material formed in the first lightly-doped region of P-type material. Accordingly, an input protection device for protecting pins of an integrated circuit is described having both bipolar and unipolar characteristics. The input protection device may be constructed as a discrete device or as part of an integrated circuit and provides for breakdown voltages in excess of a supply voltage to an integrated circuit. The characteristics, in particular the breakdown voltage, of the input protection device are alterable by adjusting its layout, in contrast to a known method of altering such characteristics by altering doping levels.

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Newtownmountkennedy, Ireland

Michael P Daly