National Semiconductor Corporation

Sun Microsystems, Inc.

Michael P Brassington

James B Burr

Reda R Razouk

Monir H El-Diwany

Prateep Tuntasood

Norman E Abt

Shi-Qing Wang

Andreas G Papaliolios

Reza Moazzami

Anne K Gregory

A method for providing a triangularly shaped I/O region on the periphery of an integrated circuit in order to reduce the amount of unused surface area on the integrated circuit is disclosed. A core region within the triangularly shaped I/O region may be either triangularly shaped or rectangularly shaped, and may include one or more metallization lines routed in a direction parallel to at least one edge of the triangularly shaped I/O region on the periphery of the integrated circuit. Alternatively, the core region may include one or more metallization lines routed in a direction parallel to at least one edge of the triangularly shaped peripheral I/O region, as well as one or more other metallization lines routed in a direction perpendicular to at least one edge of the triangularly shaped peripheral I/O region. A plurality of I/O slots located in the triangularly shaped I/O region may be triangularly, trapezoidally, or rectangularly shaped.

Alternative silicon chip geometries for integrated circuits

Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An symmetric halo device behaves like two pseudo-MOS devices in series: a 'source FET' and a 'drain FET.' If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Asymmetric low power MOS devices

An improved junction transistor requiring low power and having high performance is described. The transistor includes a substrate, a well region of a first conductivity type, and source and drain regions of a second conductivity type separated by a channel region. The transistor further includes a gate region positioned on the surface of the substrate over the channel region, and a buried region of the first conductivity type is positioned within the well region and below the surface of the substrate. The buried region has a dopant concentration of the first conductivity type sufficiently high to slow the growth of source-drain depletion regions and diminish the likelihood of punch through. The buried region may take the form of a buried electrode region or a retrograde well in alternate embodiments. The device is characterized by a gate threshold voltage of at most about 150 mV which can be electrically adjusted using back biasing or floating gate techniques.

Low power, high performance junction transistor

Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

Low threshold voltage, high performance junction transistor

Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An asymmetric halo device behaves like two pseudo-MOS devices in series: a 'source FET' and a 'drain FET.' If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Method of making asymmetric low power MOS devices

Method of making a low power, high performance junction transistor

A ferroelectric memory cell architecture in which a pair of cells is fabricated so as to share common elements, and wherein ferroelectric capacitors are fabricated overlying the associated select transistors, thereby achieving a small-area cell architecture. First level refractory metal interconnects formed prior to ferroelectric material deposition steps are utilized with subsequently formed second metallization layers to provide interconnections between the ferroelectric capacitor plates and the underlying transistor regions.

Ferroelectric memory cell arrangement having a split capacitor plate

A screening process for ferroelectric memory devices that provides a greater degree of confidence in the mechanical and thermal stability of the ferroelectric material than prior art screening processes. A correspondingly higher degree of confidence in the reliability of the screened part results.

Screening processes for ferroelectric memory devices

A circuit and technique for accessing a ferroelectric memory to read polarization states without destruction thereof. A small-amplitude positive polarity pulse is applied to the ferroelectric capacitor, and the resultant positive charge read therefrom. Thereafter, a small-amplitude negative polarity pulse is applied to the ferroelectric capacitor, and the resultant negative charge read therefrom. Because of the nonlinear hysteresis characteristics of the ferroelectric capacitor, the positive and negative readout charges are of different amplitudes. Sense amplifier circuits produce a summation of the positive and negative readout signals, with a resulting summation polarity defining the polarization state initially stored in the ferroelectric capacitor.

Nondestructive reading of a ferroelectric capacitor

A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Method of manufacturing a polysilicon emitter and a polysilicon gate

Bipolar and MOS devices are made simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Polysilicon emitter and a polysilicon gate using the same etch of

A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BiCMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconnects. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

Use of polysilicon layer for local interconnect in a CMOS or BiCMOS

A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BICMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconencts. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

Growing community of inventors

Sunnyvale, CA, United States of America

Michael P Brassington