Kenet Incorporated

Massachusetts Institute of Technology

Intersil Americas Inc.

Koninklijke Philips Corporation N.V.

Bae Systems Information and Electronic Systems Integration Inc.

Other

Michael P Anthony

Lawrence J Kushner

Edward Kohler

Gerhard Sollner

Bernard Joseph Savord

John S Fisher

Apurva N Mody

Jack Chuang

Chad M Spooner

Jeffery D Kurtze

Mckee Dunn Poland

William J Ossmann

Steven E Turner

Sunder S Kidambi

Charles R Dowdell

Joseph R Fallon

Brannon Craig Harris

Stephen Michael Grenon

Theodore Philip Fazioli

Jie Chen

William D Washkurak

Turuvekere R Gururaja

Jeff Venuti

Steven C Leavitt

Wesley Grant

Cuneyt Demirdag

T C L Gerhard Sollner

Maher Matta

Jeffrey D Kurtze

Tcl Gerhard Sollner

A system and method that uses tunnelizing for analyzing frequency spectrum. The method may include the steps of under sampling an input signal to take samples in one or more tunnels each with a tunnel bandwidth that is equal to or less than a total analysis bandwidth of the input signal; detecting one or more cyclostationary features of the input signal based on the samples; and determining one or more signal types of the one or more cyclostationary features based on the one or more cyclostationary features.

Process for tunnelized cyclostationary to achieve low-energy spectrum sensing

A system and method use tunnelizing for analyzing frequency spectrum. The method may include the steps of under sampling an input signal to take samples in one or more tunnels each with a tunnel bandwidth that is equal to or less than a total analysis bandwidth of the input signal; detecting one or more cyclostationary features of the input signal based on the samples; and determining one or more signal types of the one or more cyclostationary features based on the one or more cyclostationary features.

According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock.

Modified flying adder architecture

A Direct Current (DC) charge comparator that provides low input offset by feeding complimentary plus and minus charge inputs to a single amplification path via an alternate input path switch. Multiple sample and hold circuits at the output of the amplification path permit comparison of the result when each of the charge inputs travels down each of the paths, to determine a correction.

Charge comparator with low input offset

A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.

Boosted charge transfer circuit

An interdigitated Metal-Insulator-Metal (MIM) capacitor provides self-shielding and accurate capacitance ratios with small capacitance values. The MIM capacitor includes two terminals that extend to a plurality of interdigitated fingers separated by an insulator. Metal plates occupy layers above and below the fingers and connect to fingers of one terminal. As a result, the MIM capacitor provides self-shielding to one terminal. Additional shielding may be employed by a series of additional shielding layers that are isolated from the capacitor. The self-shielding and additional shielding may also be implemented at an array of MIM capacitors.

Metal-insulator-metal capacitors

A wide band analog-to-digital converter used in a frequency multiplexed communication system. The converter includes a plurality, M, of time-interleaved analog-to-digital converter subunits (ADC subunits). The sampling rate, FS, of the M ADC subunits is selected to locate one or more integer multiples of a Nyquist frequency of a respective subunit ADC in one or more guard bands, and/or such that one or more integer multiples of FSare also located in the guard bands.

Sampling method for time-interleaved data converters in frequency-multiplexed communications systems

A multi-channel time interleaved ADC (TIADC) provides for offset estimation and correction. The correction is accomplished through analog adjustment of offset rather than by digital correction of their outputs. In certain aspects, polarity reversal circuits may be used to further improve performance.

Background calibration of offsets in interleaved analog to digital converters

A technique for correcting charge transfer inefficiencies in a Charge Coupled Device (CCD). The basic approach is to estimate the charge entering at a given stage in a CCD pipeline, and to then determine an estimate of the error introduced by the accumulated leftover charge that will be present at a second point, farther down the pipeline. The error is then corrected by injecting a correcting charge at a third point, farther still down the CCD pipeline. The invention is used, in one embodiment, to correct the output of a charge to digital converter, although principals of the invention may be used for other types of circuits.

Correcting charge transfer inefficiency in a charge coupled analog to digital converter

A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.

Increasing charge capacity of charge transfer circuits without altering their charge transfer characteristics

An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node 'Vcmi'. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

Common-mode insensitive sampler

A circuit for improved sampler linearity, in an analog to digital converter, by taking simultaneous analog samples of an input signal V(t) and its derivative, dV/dt. The correction can be implemented as a memoryless non-linear model in the analog, digital, or mixed signal domains. Delay elements placed in the clock signal path or main input signal path can provide more precise control over the correction.

Sampler linearity by simultaneous derivative sampling

A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.

Cable gateway using a charge-domain pipeline analog to digital converter

A charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially similar to the charge input to said stage.

Growing community of inventors

Andover, MA, United States of America

Michael P Anthony