Micron Technology Incorporated

Palmchip Corporation

Tidal Systems, Inc.

Other

Michael Ou

Lyle E Adams

Meng Kun Lee

Jerry Wang

Hussam I Ramlaoui

S Jauher A Zaidi

Billy D Mills

Robin Bhagat

Hao Liu

Brian K Gutcher

Savitha Gandikota

Jon Udell

Edward Yan

Jef Munsil

Stephen Chappell

S Jauher Zaidi

A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.

Configurable buffer manager arbitration request throttling mechanism

An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.

Configurable burst optimization for a parameterizable buffer

A memory slot allocation request specifying a requested number of memory slots is received from a requestor assigned to a particular class among a plurality of classes. It is determined whether allocation of the requested number of memory slots to the requestor results in satisfaction of resource allocation constraints for the plurality of classes. The resource allocation constraints include a first and second threshold for each class that determine how many memory slots can be allocated to each class. Based on determining that allocation of the requested number of memory slots to the requestor results in satisfaction of the resource allocation constraints, the memory slot allocation request is granted. The granting of the memory slot allocation request includes allocating the requested number of memory slots to the requestor.

Class-based dynamic memory slot allocation

A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer such as, for example, number of memory banks, width of memory banks, depth of memory banks, and client bridge FIFO depth. The script converts the buffer architecture template into a hardware description language (HDL) description of a buffer manager having the parameters. Client bridges accumulate requests for memory banks in FIFO that is provided to a buffer manager upon the client bridge being granted arbitration. Accesses of memory banks may be performed one at a time in consecutive clock cycles in a pipelined manner. Client bridges and the buffer manager may operate in different clock domains. The clock frequency of the buffer manager may be increased or decreased according to requests from client devices.

Scalable, parameterizable, and script-generatable buffer manager architecture

An ATA/IDE host controllergenerated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers. An internal timing control moduleprovides either the default timing parameters or the override timing parameters to the IDE host interface, according to the programmable override control

Configurable advanced technology attachment/integrated drive electronics host controller with programmable timing registers that store timing parameters that control communications

A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

Design tool for systems-on-a-chip

The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals. Peripherals may be synchronous or asynchronous to their respective buses.

Unidirectional bus architecture for SoC applications

A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.

Chip-core framework for systems-on-a-chip

An on-the-fly error detection and correction hardware core for a mass storage hard disk drive comprises a microcode machine optimized and limited to doing Galois Field arithmetic (GF[2.sub.8 ]) in support of Reed-Solomon error detection and correction (RS-EDC). The microcode machine is implemented as a hardware core in a system-on-a-chip design that includes a general purpose core RISC-processor. A dual-input arithmetic logic unit (ALU) includes a set of basic arithmetic blocks necessary to support the RS-EDC operations, i.e., a multiplier, a dedicated adder, a general purpose adder, a divider, a log unit, a quadratic solution lookup, a cubic solution lookup, and a move datapath. The operations and outputs of all the basic arithmetic blocks are presented in parallel to an op-code selector. The selected output is routed back for deposit to one of eight general purpose registers (R0-R7). A set of up to eight syndrome registers (S0-S7) can be selectively routed along with R0-R7 through a pair of ALU-input selectors. A microinstruction register allows a destination register decoder to be controlled, instruction-by-instruction, as well as the ALU input and output selectors. The microcode program is stored in a ROM-type structure that is indexed by a program counter. A flow control selector allows either the next microprogram address (+1) to be selected from an incrementer, or a branch address to be selected from a jump table.

Growing community of inventors

Newark, CA, United States of America

Michael Ou