Marvell International Limited

Intel Corporation

Marvellworld Trade Ltd.

Marvell Israel (misl) Ltd.

Marvell Isreal Ltd. (m.i.s.l.)

Michael Orr

Nafea Bishara

Gad Hutt

Mohan J Kumar

Nafea Bshara

Tsahi Daniel

David Melman

Mrittika Ganguli

Yadong Li

Yuval Cohen

Anjaneya Reddy Chagam Reddy

Dan Biederman

Vitaly Vovnoboy

Uri Safrai

Ronen Tausi

Alon Harel

Naftali Tannin

Zion Shohet

Eugene Zetserov

Adi Sapir

Victor Ryabchin

Technologies for load balancing a storage network include a system. The system includes circuitry to adjust routing rules in a network interface controller to deliver a packet from one of multiple uplinks to one of any physical functions, circuitry to remap, in response to a failure of a switch, a port from one physical function to another physical function, and circuitry to communicate control data between a software defined network controller and one or more agents in one or more host endpoints with a hierarchical distributed hashing table.

Technologies for load balancing a network

Various systems and methods for implementing a flexible packet processing mechanism are provided herein. A network interface device for implementing flexible packet processing includes a packet parser to: receive a packet; and determine from analyzing the packet, a corresponding processing element that is used to process the packet; and a coordinator circuit to: determine whether the processing element is active in a computing unit; load the processing element when it is not active; and forward the packet to the processing element.

Flexible packet processing

Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.

Intelligent packet aggregation

The present disclosure describes techniques for hardware acceleration for routing programs. In some aspects communications between a routing determination program and a packet router are monitored in a router, both the routing determination program and the packet router being part of a software layer of the router. The communications include the routing determination program providing configuration data to the packet router. Based on the monitored communications, a packet processor is changed to reflect the configuration data, the packet processor being part of a hardware layer of the router. The packet processor performs packet routing operations of receiving packets, determining the next routers in the paths to the target destinations of the packets, and sending the packets to the next routers independent of the software layer.

Hardware acceleration for routing programs

A method of processing one or more packets includes receiving, at a first processing unit, a first packet including first information bits. The first information bits indicate a first control parameter. The method also includes determining whether the first control parameter will be utilized to process the first packet in at least a second processing unit and, at least partially in response to determining that the first control parameter will not be utilized to process the first packet in at least the second processing unit, replacing one or more bits of the first information bits in the first packet with second information bits. The second information bits indicate a second control parameter. The method also includes providing the first packet including the second information bits to the second processing unit.

Using standard fields to carry meta-information

Systems, methods, and other embodiments associated with controlling transmission of packets over a link aggregation group (LAG) using policies arranged in a tree hierarchy are described. According to one embodiment, a device includes a decision logic configured to manage transmission of packets over a link aggregation group by individually evaluating the packets according to a plurality of policies arranged into a tree hierarchy. The link aggregation group includes a plurality of interfaces connected to a remote device. The decision logic is configured to select one of the plurality of interfaces of the link aggregation group for each of the packets by using the plurality of policies. A transmission logic configured to control transmission of each of the packets according to which interface of the link aggregation group is selected for each of the packets as a result of evaluating the packets using the plurality of policies.

Method and apparatus for controlling transmission of packets over a link aggregation group

In one embodiment, an apparatus comprises a queue scheduler configured to schedule frames to be buffered through one of a plurality of queues wherein each queue is designated to buffer frames having a pre-assigned priority. Congestion control logic is configured to change the pre-assigned priority of one or more frames before the one or more frames are scheduled by the queue scheduler to cause the one or more frames to be buffered in a different queue than the queue designated for the pre-assigned priority.

Congestion avoidance for network traffic

A packet processor includes an extraction circuit, a lookup circuit, an assignment circuit, a rule matching circuit, and an action circuit. The extraction circuit generates a first set of values based on a first packet. The lookup circuit stores metadata values. Each of the metadata values corresponds to a respective metadata identifier. The assignment circuit assigns a first metadata identifier to the first packet. The lookup circuit selectively retrieves a first metadata value that corresponds to the first metadata identifier. The rule matching circuit selects a first rule from among a predetermined set of rules based on the first set of values and the first metadata value. The action circuit identifies a first action specified by the first rule and performs the first action. The first action includes modifying the first metadata value of the plurality of metadata values.

Mechanism for wire-speed stateful packet inspection in packet processors

System and methods are provided for performing deep packet inspection of data packets. An example system includes a packet forwarding component and a virtual machine component. The packet forwarding component is configured to receive data packets for transmission and to select one or more of the data packets based at least in part on a first set of rules for deep packet inspection. The virtual machine component is configured to perform deep packet inspection on the selected data packets according to a second set of rules to determine whether the selected data packets are allowed for transmission. The packet forwarding component is further configured to transmit the selected data packets when the selected data packets are allowed for transmission after the deep packet inspection.

Systems and methods for deep packet inspection with a virtual machine

In aspects of enhanced network access-control credentials, a network access device includes a network interface for data communication with network-connected devices via a network. The network access device implements an access control manager that receives a network access request from a requesting device to access the network, where the network access request includes authentication credentials. The access control manager can then modify the network access request to generate a modified network access request, and initiate communication of the modified network access request to an authentication server that authenticates the requesting device to the network based on the modified network access request.

Enhanced network access-control credentials

In one embodiment, a method performs, by at least a processor, a computer networking function as controlled, at least in part, by a configuration for a networking device. Source commands are received to establish the configuration, wherein the source commands are written in a source command language. The source commands are translated from the source command language to target commands written in a target command language, wherein the translation is based, at least in part, on a function to function translation model. The configuration is then established by executing at least the target commands.

Model driven command language translator

In one or more embodiments, attributes other than a supplicant's MAC address can be used for the user name in the authentication process in a network computing environment. In at least some embodiments, doing so utilizes an association structure, such as a table, that is already resident at the authentication server. By using attributes other than a supplicant's MAC address, various matching scenarios can be provided by the authentication server in which authentication or authorization takes place responsive to satisfying conditions defined in the authentication server's association or database. Furthermore, a variety of non-authentication scenarios can be supported using the authentication server's association.

Authentication of computing devices using augmented credentials to enable actions-per-group

Systems, methods, and other embodiments associated with controlling the flow of packets in a network are described. According to one embodiment, an apparatus includes a transceiver and a flow logic. The flow logic is configured to control the transceiver to transmit a frame to a downstream device by determining whether the frame matches a predetermined pattern. The predetermined pattern identifies a source of frames. The predetermined pattern specifies an action to perform for frames received from the source that are to be transmitted to the downstream device. The flow logic is also configured to control the transceiver to transmit a frame to a downstream device by, in response to determining that the frame matches the predetermined pattern, controlling transmission of the frame to the downstream device according to the action specified by the predetermined pattern.

Method and apparatus for controlling the flow of packets in a data network

A network device including a first and second processors. The first processor: receives first and second packets; and selects some of the second packets according to contents of the second packets and sampling criteria. The second processor operates in first and second modes. While operating in the first mode, the second processor learns a traffic pattern of the first packets through the network device. While operating in the second mode, the second processor compares a traffic pattern of the some of the second packets to the traffic pattern of the first packets to determine whether the second packets are associated with an attack on the network device. In response to determining the second packets are not associated with an attack on the network device, the second processor updates the patterns of the first packets based on a characteristic of the some of the second packets.

Growing community of inventors

Sunnyvale, CA, United States of America

Michael Orr