Oracle International Corporation

Oracle America, Inc.

Other

Michael Oliver McCracken

Pranay Koka

Herbert Dewitt Schwetman, Jr

Ashok V Krishnamoorthy

Xuezhe Zheng

David Alexander Munday

Jan Lodewijk Bonebakker

Xuexhe Zheng

Ronald Ho

John E Cunningham

David K McElfresh

Kannan Raj

Jose Renau Ardevol

The disclosed embodiments provide a system in which a processor chip accesses an off-chip cache via silicon photonic waveguides. The system includes a processor chip and a cache chip that are both coupled to a communications substrate. The cache chip comprises one or more cache banks that receive cache requests from a structure in the processor chip optically via a silicon photonic waveguide. More specifically, the silicon photonic waveguide is comprised of waveguides in the processor chip, the communications substrate, and the cache chip, and forms an optical channel that routes an optical signal directly from the structure to a cache bank in the cache chip via the communications substrate. Transmitting optical signals from the processor chip directly to cache banks on the cache chip facilitates reducing the wire latency of cache accesses and allowing each cache bank on the cache chip to be accessed with uniform latency.

Accessing an off-chip cache via silicon photonic waveguides

The disclosed embodiments provide a system that uses broadcast-based TLB sharing to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an optical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the optical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the optical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect

In a multi-chip module (MCM), optical waveguides in a first plane convey modulated optical signals among integrated circuits (which are sometimes referred to as 'chips'). Moreover, an optical-butterfly switch, optically coupled to the optical waveguides, dynamically allocates communication bandwidth among the integrated circuits. This optical-butterfly switch includes optical components in the first plane and a second plane, and optical couplers that couple the modulated optical signals to and from the first plane and the second plane. In this way, the MCM communicates the modulated optical signals among the integrated circuits without optical-waveguide crossings in a given plane.

Butterfly optical network with crossing-free switches

The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a directory controller that manages a distinct portion of the system's address space. During operation, a first node receives a request for a page-table entry that is located at a physical address that is managed by the first node. The first node accesses its directory controller to retrieve the page-table entry, and then uses the page-table entry to calculate the physical address for a subsequent page-table entry. The first node determines the home node (e.g., the managing node) for this calculated physical address, and sends a request for the subsequent page-table entry to that home node.

Distributed page-table lookups in a shared-memory system

The disclosed embodiments provide techniques for reducing address-translation latency and the serialization latency of combined TLB and data cache misses in a coherent shared-memory system. For instance, the last-level TLB structures of two or more multiprocessor nodes can be configured to act together as either a distributed shared last-level TLB or a directory-based shared last-level TLB. Such TLB-sharing techniques increase the total amount of useful translations that are cached by the system, thereby reducing the number of page-table walks and improving performance. Furthermore, a coherent shared-memory system with a shared last-level TLB can be further configured to fuse TLB and cache misses such that some of the latency of data coherence operations is overlapped with address translation and data cache access latencies, thereby further improving the performance of memory operations.

Using a shared last-level TLB to reduce address-translation latency

The disclosed embodiments provide a system that uses broadcast-based TLB-sharing techniques to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an electrical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the electrical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the electrical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with electrical interconnect

Combining a remote TLB lookup and a subsequent cache miss into a single coherence operation

A method for arbitration in an arbitration domain. The method includes: receiving, by each node of a plurality of nodes in the arbitration domain, an arbitration request from each sending node of the plurality of nodes in the arbitration domain, where the plurality of nodes in the arbitration domain each use a shared data channel to send data to a set of receiving nodes; assigning, by each node in the arbitration domain, consecutive time slots to each sending node based on a plurality of priorities assigned to the plurality of nodes in the arbitration domain; for each time slot: sending, from the arbitration domain, a switch request to a receiving node designated by the sending node, where the receiving node is in the set of receiving nodes; and sending, by the sending node, data to the receiving node via the shared data channel during the time slot.

Two-phase arbitration mechanism for shared optical links

In a multi-chip module (MCM), integrated circuits are coupled by optical waveguides. These integrated circuits receive optical signals from a set of light sources which have fixed carrier wavelengths. Moreover, a given integrated circuit includes: a transmitter that modulates at least one of the optical signals when transmitting information to at least another of the integrated circuits; and a receiver that receives at least one modulated optical signal having one of the carrier wavelengths when receiving information from at least the other of the integrated circuits. Furthermore, the MCM includes tunable drop filters optically coupled to the optical waveguides and associated integrated circuits, wherein the tunable drop filters pass adjustable bands of wavelengths to receivers in the integrated circuits. Additionally, control logic in the MCM provides a control signal to the tunable drop filters to specify the adjustable bands of wavelengths.

Arbitrated optical network using tunable drop filters

A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address.

Processor-bus-connected flash storage paging device using a virtual memory mapping table and page faults

In a multi-chip module (MCM), integrated circuits are coupled by optical waveguides. These integrated circuits receive optical signals from a set of tunable light sources. Moreover, a given integrated circuit includes: a transmitter that modulates at least one of the optical signals when transmitting information to at least another of the integrated circuits; and a receiver that receives at least one modulated optical signal having a given carrier wavelength associated with the given integrated circuit when receiving information from at least the other of the integrated circuits. Furthermore, control logic in the MCM provides a control signal to the set of tunable light sources to specify carrier wavelengths in the optical signals output by the set of tunable light sources, thereby defining routing of at least the one of the optical signals in the MCM during communication between at least a pair of the integrated circuits.

Optical network with tunable optical light sources

In a multi-chip module (MCM), integrated circuits are coupled by optical waveguides. These integrated circuits receive optical signals from a set of light sources which have fixed carrier wavelengths. Moreover, a given integrated circuit includes: a transmitter that modulates at least one of the optical signals when transmitting information to at least another of the integrated circuits; and a receiver that receives at least one modulated optical signal having one of the carrier wavelengths when receiving information from at least the other of the integrated circuits. Furthermore, the MCM includes switchable drop filters optically coupled to the optical waveguides and associated integrated circuits, wherein the switchable drop filters pass adjustable bands of wavelengths to receivers in the integrated circuits. Additionally, control logic in the MCM provides a control signal to the switchable drop filters to specify the adjustable bands of wavelengths.

Optical network with switchable drop filters

A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel.

Time division multiplexing based arbitration for shared optical links

A system for optical data communication, including: a first sending node including a first data item for transmission to a first receiving node during a first timeslot; a second sending node including a second data item for transmission during a second timeslot; a first optical data link (ODL) and a second ODL; a first output switch configured to switch the first data item from the first sending node onto the first ODL during the first timeslot; a second output switch configured to switch the second data item from the second sending node onto the first ODL during the second timeslot; an optical coupler connecting the first and second ODL; and a first input switch operatively connecting the first receiving node with the second ODL and configured to switch the first data item from the second ODL to the first receiving node during the first timeslot.

Data channel organization for a switched arbitrated on-chip optical network

A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Growing community of inventors

Austin, TX, United States of America

Michael Oliver McCracken