Lsi Logic Corporation

Xilinx, Inc.

International Business Machines Corporation

Lsi Corporation

Michael O Jenkins

Francois Ducaroir

Karl S Nakamura

Cheng-Hsiang Hsieh

Stephen A Jove

Damon W Finney

Brett D Hardy

Christopher J Borrelli

Jacobus C Van Peppen

Jeffrey A Hall

Amar Amin

Shawn Nikoukary

Andrew Dale Walls

Yohan Usthavia Frans

James Karp

Ephrem C Wu

Klaas Berend Klaassen

Alan S Fiedler

Vassili Kireev

Hongtao Zhang

Joseph M Mosley

Geoffrey Zhang

Stephen Douglas Weitzel

Paul Wingshing Chung

Alan C Wong

Jack A Dorler

Donald J Lang

Prashant K Singh

Mark J Marlett

Dale Brian Chapman

Jeffrey S Kueng

Paik Saber

Peter Paul Urbisci

Narasimhareddy L Annapareddy

Michael James Rayfield

Donald C Grillo

David N Mora

David A Plomgren

Hong Sik Ahn

Larry B Kessler

Michael Okronglis

Song C Liang

Ivan O Madrigal

Murtuza Z Cutleriwala

John R Carrel

A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.

Method and system for correlation of a behavioral model to a circuit realization for a communications system

In an exemplary system, a first sampling circuit is coupled to a clock module to receive values therefrom. A second sampling circuit is coupled to the clock module to receive the values therefrom. The first sampling circuit includes a first converter, a first phase interpolator, and a first sampler. The first converter is coupled to replace the values with first replacement values for input to the first phase interpolator. The second sampling circuit includes a second converter, a second phase interpolator, and a second sampler. The second converter is coupled to replace the values with second replacement values for input to the second phase interpolator.

Pre-distortion for a phase interpolator with nonlinearity

A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.

Circuits for and methods of implementing a receiver in an integrated circuit device

In an apparatus, a receiver includes a clock data recovery module to provide a dense distribution of waveform edges across an adjustment range, and an eye scan circuit to obtain samples at a first sample position and a second sample position to provide an error count for a sample count for the samples. An eye scan module, coupled to the receiver, is configured to: scan for the samples at the first sample position of a first type for each of a plurality of sample positions of a second type to obtain an error count for a sample count for each of the plurality of sample positions; locate a threshold BER from the scan; determine an amount and a direction of a sample offset at the threshold BER from a reference location; and adjust either the first sample position or the second sample position responsive to the amount and the direction.

Offset calibration and adaptive channel data sample positioning

An embodiment of an apparatus for nonlinearity compensation is disclosed. For an embodiment, a pre-distorter is coupled to receive a first signal. The pre-distorter is configured to convert first values of the first signal into second values for a second signal. The pre-distorter includes a converter for converting the first values to the second values. A phase interpolator is coupled to receive the second signal. The second values are associated with nonlinearity of the phase interpolator. The phase interpolator is configured to provide an interpolated output from the second signal. The second signal is adjusted for the nonlinearity of the phase interpolator by use of the second values.

An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

Interposer having an inductor

In accordance with some embodiments, an integrated circuit device comprises a circuit configured to provide a sense signal representing a dynamic power requirement of the circuit to a first sense node, a first sense switch coupled between the first sense node and a first die bump, and a sense switch controller configured to provide a control signal to the first sense switch.

Power supply regulation and optimization by multiple circuits sharing a single supply

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

Methods for avoiding parasitic capacitance in an integrated circuit package

Device for avoiding parasitic capacitance in an integrated circuit package

A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

Serial data transmitter with bit doubling

An over-voltage protected integrated circuit is provided, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.

ESD protection circuit for low amplitude signals

A data transmission circuit for transmitting a data stream includes a voltage supply terminal, a resistively terminated, controlled-impedance transmission line and an inductor coupled between the voltage supply terminal and the controlled-impedance transmission line.

Transmission circuit having an inductor-assisted termination

A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver. A test method involves asserting the test signal, providing serial input test data to a serial data input port, receiving serial output test data from a serial data output port, and comparing the serial output test data to the serial input test data. A match between the serial output test data and the serial input test data verifies proper operation of the serial data transceiver.

Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method

A serial data transceiver architecture and test method are presented for measuring the amount of jitter within a serial data stream. A transmitter of the transceiver receives parallel input data at a transmit data input port, converts the parallel input data to a serial data stream having data windows separated by data transition periods, and produces the serial data stream at a transmitter output port. A receiver of the transceiver receives a serial data stream at a receiver input port, converts the serial data stream to parallel output data, and provides the parallel output data at a receive data output port. The receiver includes a deserializer which receives the serial data stream, recovers the transmit clock signal used to transmit the serial data from the serial data stream, generates a timing signal based upon the recovered transmit clock signal, samples the serial data stream using the timing signal in order to recover the data from the serial data stream, aligns the deserialized data into parallel units, and provides the resulting parallel data at the receive data output port. The deserializer samples the serial data stream within each data window dependent upon the duty cycle of the timing signal. The deserializer varies the duty cycle of the timing signal according to a received control signal in order to facilitate measurement of the amount of jitter within the serial data stream.

Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream

One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent. Each transmit unit comprises a receiver operably coupled between an input port and an output port, and a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. Also included are a transmitter which receives parallel data and transmits a serial data stream. The parallel data are received concurrently with the serialized data being received. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream.

High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network

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San Jose, CA, United States of America

Michael O Jenkins