Iroc Technologies

Synopsys, Inc.

Michael Nicolaidis

Slimane Boutobza

Silmane Boutobza

The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (), having at least an output (A); a circuit () generating an error control code for said output, and a storage element () provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

Logic circuit protected against transient disturbances

One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.

Runtime programmable BIST for testing a multi-port memory device

Logic circuit protected against transitory perturbations

A circuit for evaluating characteristics of duration and/or shape of an electric pulse induced in an element of an integrated circuit comprising an assembly of elements, each element being likely to receive an occasional external disturbance generating an electric pulse in the element, and a measurement circuit connected to the elements to determine said characteristics of an electric pulse generated in one of the elements.

Evaluation of the characteristics of electric pulses

The invention concerns a data storage method enabling error detection and correction in an organized storage for reading and writing words of a first number (m) of bits and optionally for modifying only part of such a word, comprising the following steps which consist in: associating an error detection and correction code with a group of a second number (k&#x2267;1) of words; and at each partial writing in the group of words, calculating a new code of the modified group of words; performing a verification operation and, if an error occurs, carrying out an error correction of the modified word and/or of the new code.

Data storage method with error correction

The invention CONCERNS a device for reconfiguring an assembly of N basic electronic modules associated with k redundant modules comprising: N multiplexers each having a first terminal (d) capable of being connected to k+1 second terminals connected to the k+1 input/output terminals of a sequenced group of modules consisting of a basic module (U) and k other modules; N+k triggers (F) indicating a good or faulty condition of one of the N+k modules; and logic means associated with each multiplexer of rank j, where j is an integer ranging between 0 and N, to determine the number of triggers of rank 0 to j indicating a faulty condition, to determine the number of modules of the sequenced group associated with the module of rank j, to be counted to find a number of good modules equal to the first number, and to convert the first terminal of the multiplexer to its second terminal of rank equal to the second number.

Growing community of inventors

Saint Egreve, France

Michael Nicolaidis