Infineon Technologies Ag

Infineon Technologies Austria Ag

Michael Nelhiebel

Rainer Pelzer

Robert Illing

Werner Robl

Bernhard Weidgans

Stefan Woehlert

Sven Lanzerstorfer

Thomas Detzel

Stefan Decker

Klemens Pruegl

Ravi Keshav Joshi

Carsten Schaeffer

Sven Schmidbauer

Michael Rogalli

Michael Fugger

Marianne Mataln

Johann Gross

Maximilian Krug

Andrea Baschirotto

Dieter Haerle

Alexander Mayer

Johann Gatterbauer

Christian Djelassi

Christian Djelassi-Tscheck

Klaus Goller

Kurt Matoy

Jakob Kriz

Olaf Heitzsch

Bernhard Auer

Arno Zechmann

Siegfried Roehl

Joerg Busch

Cristian Mihai Boianceanu

Petar Fanic

Norbert Mais

Silvia Larisegger

Axel Buerke

Heiko Assmann

Achim Osterloh

Sabine Reither

Johannes Zechner

Katrin Albers

Bernhard Zagar

Sergio De Gasperi

Marianne Kolitsch

Axel Bürke

A circuit includes a power transistor having a main current path between a first supply node and an output pin for connecting a load. A resistance formed by a chip metallization is arranged between the main current path of the power transistor and the output pin. The circuit includes a current measuring circuit coupled to the power transistor and including a sense transistor coupled to the power transistor. The current measuring circuit delivers a measurement current representing a load current flowing through the power transistor. An amplifier circuit generates an amplifier output signal representing the voltage across the resistance, and a control circuit outputs a signal representing the measurement current in a first mode and a signal dependent on the amplifier output signal in a second mode.

Current measuring circuit

In some examples, a device includes a power structure and a sensing structure that is electrically isolated from the power structure. The device also includes processing circuitry configured to determine whether the sensing structure includes a prognostic health indicator, wherein the prognostic health indicator is indicative of a health of the power structure.

Prognostic health management for power devices

A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.

Semiconductor device power metallization layer with stress-relieving heat sink structure

According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.

Semiconductor device and a method of forming the semiconductor device

A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

Barrier for power metallization in semiconductor devices

A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

Method of manufacturing a semiconductor device having a power metallization structure

A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %.

Semiconductor device with copper structure

Power metallization structure for semiconductor devices

A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

Semiconductor device with compressive interlayer

A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

Semiconductor device having a copper element and method of forming a semiconductor device having a copper element

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor body includes a load current component having a load current transistor area and a sensor component having a sensor transistor area. The load current transistor area and the sensor transistor area share a same transistor unit construction. The load current transistor area includes first and second transistor area parts, and the sensor transistor area includes a third transistor area part. The first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.

Semiconductor device having a load current component and a sensor component

Self-organizing barrier layer disposed between a metallization layer and a semiconductor region

A semiconductor device includes a substrate, a structured interlayer on the substrate and having defined edges, and a structured metallization on the structured interlayer and also having defined edges. Each defined edge of the structured interlayer neighbors one of the defined edges of the structured metallization and runs in the same direction as the neighboring defined edge of the structured metallization. Each defined edge of the structured interlayer extends beyond the neighboring defined edge of the structured metallization by at least 0.5 microns so that each defined edge of the structured metallization terminates before reaching the neighboring defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature.

Compressive interlayer having a defined crack-stop edge extension

A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor body includes a load current component having a load current transistor area and a sensor component including a sensor transistor area. The sensor transistor area has first and third transistor area parts differing from a second transistor area part between the first and third transistor area parts by a sensor transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and third transistor area parts by the sensor transistor area element being absent in the second transistor area part.

Semiconductor device including self-protecting current sensor

An electrically conductive element includes an electrically conductive material and a plurality of inclusions of a phase change material. The phase change material has a phase transition temperature Tc between 150&#xb0; C. and 400&#xb0; C. The inclusions are separated from each other and are embedded in the electrically conductive material.

Electrically conductive element, power semiconductor device having an electrically conductive element and method of manufacturing a power semiconductor device

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Villach, Austria

Michael Nelhiebel