Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Synopsys, Inc.

Philips Electronics North America Corporation

Michael N Misheloff

Calvin T Gabriel

Subhas Bothra

Milind Ganesh Weling

Harold J Levy

Xin Wang

Sabita Jasty

Michael D Grossman

Paul R Findley

Thomas J Schaefer

David C Chapman

Athanasius W Spyrou

Harish K Sarin

Osman E Akcasu

Bruce S Seiler

Balaji Krishnamachary

Michael R Grossman

Andrew J McNelly

Clementina Bures

Marie C Salet

Peter Liebmann

An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Generating a base curve database to reduce storage cost

A method is presented for generating a timing model for a logic cell. Output load indices (Load , Load , . . . ,Load ) are selected which specify output load for the first logic cell. Input ramp indices (IR , IR , . . . ,IR ) are selected which specify input ramp for the first logic cell. Baseline output ramp values (OR &lsqb;j,k&rsqb;) are generated for each output load index (Load ) and input ramp index (IR ) pair. In order to take into account process, power and temperature variations, scaling factors are used to scale the indices. For example these scaling factors can be utilized for many different logic cells in a cell library. In one embodiment, the output load indices are scaled by a first scaling factor (&lgr;). The input ramp indices are scaled by a second scaling factor (&rgr;). Scaled output ramp values (OR &lsqb;j,k&rsqb;) are generated for each scaled output load index and scaled input ramp index pair. A third scaling factor (&ggr;) is used to generate the scaled output ramp values (OR &lsqb;j,k&rsqb;). Additionally, delay values can be generated as well. Specifically, baseline delay values (Delay &lsqb;j, k&rsqb;) are generated for each output load index (Load ) and input ramp index (IR ) pair. Scaled delay values (Delay &lsqb;j, k&rsqb;) are generated for each scaled output load index and scaled input ramp index pair.

Method of scaling table based cell library timing models in order to take into account process, temperature and power supply

A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Methods for forming co-axial interconnect lines in a CMOS process for high speed applications

A method for making a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer, and a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer is provided. The method includes forming a lower metallization layer and a lower dielectric layer over the lower metallization layer. A metallization line is formed over the lower dielectric layer with an upper dielectric layer over the metallization line. An upper metallization layer is then formed over the upper dielectric layer. After this is completed, oxide spacers are formed along the sides of the lower dielectric layer, the metallization line, and the upper dielectric layer. Finally, an encapsulating metallization layer is formed over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield and the metallization line defines an inner conductor of an RF line.

Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications

A waveguide structure and method of making a waveguide for communicating optical signals is provided. The waveguide structure is made using standard CMOS fabrication operations and is integrated on the same chip having digital CMOS circuitry. An example method of making the waveguide includes forming a contact through a dielectric layer down to a substrate and coating sidewalls of the contact with a first metallization coating. The contact is then filled with a dielectric material. A partial waveguide structure is formed over the first metallization coating and the dielectric material of the contact. The partial waveguide structure is defined by a waveguide dielectric structure and a second metallization coating that is defined over the waveguide dielectric structure. A third metallization coating is then formed to define spacers along sides of the partial waveguide structure, the first metallization coating, the second metallization coating. The third metallization coating is configured to complete the waveguide structure that is filled with the waveguide dielectric structure. Optical signals can then be propagated through the waveguide structure and can be interfaced with other CMOS digital circuitry.

Waveguide structures integrated with standard CMOS circuitry and methods for making the same

In accordance with the preferred embodiment of the present invention, a logic cell library is built. Within the logic cell library a timing model for a first logic cell is generated. In order to generate the timing model a number of indices which specify input ramp for the first logic cell is selected. Also, a number of indices which specify output load for the first logic cell is selected. Also selected are a minimum value for the input ramp and a maximum value for the input ramp. A maximum output load for the timing model is calculated. This is done by calculating, for every input transition in the logic cell which causes an output transition, an intermediate value to be an output load value which results in the first logic cell producing an output signal to the first logic cell which has the maximum value for the input ramp when an input signal to the logic cell has the minimum value for the input ramp. The maximum output load is chosen to be a minimum of the calculated intermediate values.

Determining maximum load index for tabular timing models

The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.

Method and apparatus for verifying signal timing of electrical circuits

In a computer implemented circuit simulator, a method is provided for measuring energy consumption of a circuit under test during a measurement interval. The method comprises a series of computer implemented steps. A supply voltage is applied to the circuit under test. A current flowing through the circuit under test is then measured. A mirror voltage, representative of the value of the current, is generated. A capacitor is charged, with a power parameter voltage equal to the product of the supply voltage and the mirror voltage, during the measurement interval. An accumulated voltage is measured across the capacitor, wherein the accumulated voltage is representative of energy consumed by the circuit under test.

Method of measuring energy consumption in a circuit simulator

A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell's power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period. The clocked accumulation of power usage enables easy detection of whether the peak rate of power consumption during the simulation time exceeds a specified threshold (e.g., a threshold associated with a particular power bus design). Thus, data generated by the power usage simulation may be used, either directly or indirectly to determine that the simulated logic circuit requires a larger power bus design, or that the logic circuit should be modified so as to reduce its peak power usage rate.

Slew rate based power usage simulation and method

A method determines approximate propagation delay through logic devices within a library. Each logic cell within the library is characterized at baseline conditions to obtain parameters for each logic cell which define propagation delay through each logic cell at the baseline conditions. A subset of the logic cells are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells within the library in order to approximate changes in propagation delay through each logic cell resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.

Timing model and characterization system for logic simulation of

A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value. The second formula also varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device.

A method estimates source resistance for a transistor. A substrate region under a gate for the transistor is modeled as a gate region having a uniform resistivity .rho..sub.g. A source of the transistor is modeled as a source region having a uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s1 are used to calculate a first current from the source of the transistor to a drain of the transistor. The source of the transistor is then modeled as a source region having another uniform resistivity .rho..sub.s2. The uniform resistivity .rho..sub.s2, is different in value than uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s2 are used to calculate a second current from the source of the transistor to a drain of the transistor. The uniform resistivity .rho..sub.s1, the uniform resistivity .rho..sub.s2, the first current and the second current are used to calculate the source resistance for the transistor.

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Dublin, CA, United States of America

Michael N Misheloff