Ventana Micro Systems Inc.

Michael N Michael

John G Favor

Vihar Soneji

David S Oliver

A microprocessor includes a prediction unit (PRU) that continuously predicts a sequence of fetch block start addresses (FBSAs) that specify a corresponding sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op cache (MOC) having MOC entries (MEs). The PRU installs into the MOC a loop body ME using a first FBSA value that specifies the loop body ME, instructs a fusion engine to build an unrolled loop multi-FBlk ME (ULP-MF-ME) using F copies of the loop body ME, installs the ULP-MF-ME using the same first FBSA value, detects a multiple-hit in the MOC on both the loop body ME and the ULP-MF-ME, and instructs a fetch unit to fetch from the MOC a number of copies of the ULP-MF-ME equal to an unrolled loop iteration count of the ULP-MF-ME and instructs the fetch unit to fetch the loop body ME until the loop exits.

Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fetch block macro-op cache entry and loop body macro-op cache entry used to build same

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), and a fusion engine. A FBlk comprises a sequential run of architectural instructions. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded and includes training fields, updated by the PRU as the PRU predicts the ME in the program instruction stream. The PRU, in response to detecting that the training fields of an ME indicate the ME has been a loop body ME that has exhibited a consistent loop iteration count within the program instruction stream, requests the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is at least two.

Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-op cache entries

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a decode unit, and a fusion engine. Each ME indicates whether it is a single-FBlk ME (SF-ME) that holds MOPs associated with a single FBlk whose architectural instructions have been decoded into the MOPs of the SF-ME or a multi-FBlk ME (ME-ME) that holds MOPs associated with multiple FBlks whose architectural instructions have been decoded into the MOPs of the MF-ME. For each FBlk of one or more FBlks in the program instruction stream: the decode unit decodes the architectural instructions of the FBlk into MOPs, and the fusion engine builds a SF-ME in the MOC using the decoded MOPs, and the fusion engine builds a MF-ME in the MOC using the MOPs of a series of SF-MEs.

Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process

A microprocessor includes a macro-op (MOP) cache (MOC) that holds MOC entries (MEs), including single-fetch block MEs (SF-MEs) and multi-fetch block MEs (MF-MEs), comprising MOPs decoded from architectural instructions. A prediction circuit generates fetch block (FBlk) start addresses (FBSAs) to make predictions of a sequence of FBlks fetched from an instruction cache and MEs fetched from the MOC. A back end detects that execution of a MOP of an MF-ME needs an abort and generates an abort request. A control circuit flushes all the MF-ME's MOPs and signals the prediction circuit to restart prediction at the MF-ME's FBSA. For each current FBSA of N current FBSAs used to make N predictions starting with the FBSA of the MF-ME, the prediction circuit ignores a hit on any MF-ME and instead, if the current FBSA hits on an SF-ME, predicts the SF-ME, and otherwise predicts a FBlk at the current FBSA.

Microprocessor that performs partial fallback abort processing of multi-fetch block macro-op cache entries

A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).

Prediction unit that predicts successor fetch block start address of multi-fetch block macro-op cache entry

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a fusion engine. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU detects a loop body ME within the program instruction stream, accumulates loop iteration count information about a series of instances of a loop on the loop body ME in the program instruction stream, updates a consistency counter of the loop body ME while accumulating the loop iteration count information, and in response to detecting that the consistency counter has reached a threshold, instructs the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is a loop unroll factor that is at least two.

Microprocessor that builds inconsistent loop that iteration count unrolled loop multi-fetch block macro-op cache entries

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs). An ME is either a single-FBlk ME (SF-ME) that holds MOPs associated with a single FBlk or a multi-FBlk ME (ME-ME) that holds MOPs associated with multiple FBlks. The PRU instructs a fusion engine to build a first MF-ME using the MOPs of a first set of two or more MEs when training fields of the first set of MEs indicate the first set appear as a first consistent sequence and instructs the fusion engine to build a second MF-ME using the MOPs of the first MF-ME and a third ME when the training fields of the first MF-ME indicate the first MF-ME and the third ME appear as a second consistent sequence within the program instruction stream.

Microprocessor that extends sequential multi-fetch block macro-op cache entries

A microprocessor includes a macro-op (MOP) cache (MOC) having MOC entries (MEs) holding MOPs. An instruction fetch circuit fetches from the MOC the MOPS of an ME for execution, and a back-end detects that a MOP of the ME is causing a need for an abort type within a predetermined subset of abort types. A control circuit uses a location within the ME of the abort-causing MOP to determine an abort point that separates the ME into a former portion and a latter portion, flushes the MOPs of the latter portion of the ME, and allows the MOPs of the former portion of the ME to execute. After the flush of the MOPs of the latter portion of the ME, the microprocessor re-fetches and executes the MOPs of the latter portion of the ME but does not re-execute the MOPs of the former portion of the ME.

Microprocessor that performs mid-macro-op cache entry restart abort processing

A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.

Prediction unit that predicts branch history update information produced by multi-fetch block macro-op cache entry

A prediction unit includes a first predictor that provides an output comprising a hashed fetch address of a current fetch block in response to an input. The first predictor input comprises a hashed fetch address of a previous fetch block that immediately precedes the current fetch block in program execution order. A second predictor provides an output comprising a fetch address of a next fetch block that immediately succeeds the current fetch block in program execution order in response to an input. The second predictor input comprises the hashed fetch address of the current fetch block output by the first predictor.

Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), and a fusion engine. An ME includes an expected next ME identifier and a counter, updated by the PRU as it predicts the ME in the program instruction stream, that is an indicator of consistency of sequence in the program instruction stream of the ME and an ME indicated by the expected next ME identifier. The PRU detects that each of the counters of N MEs indicate a highly consistent sequence of the N MEs and a final ME identified by the expected next ME identifier of a last ME in the sequence and instructs the fusion engine to use the MOPs of the N MEs and of the final ME to build in the MOC a sequential multi-FBlk ME.

Microprocessor that builds sequential multi-fetch block macro-op cache entries

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs). An ME holds MOPs into which architectural instructions of one or more FBlks are decoded. The PRU receives a detection of a first instance in which execution of an ME caused a need for an abort and in response resets a counter of the ME. Subsequently, the PRU increments the counter when the PRU predicts the ME is present, invalidates the ME in response to detecting a predetermined number of instances in which execution of the ME caused a need for an abort before the counter reaches a threshold, and retains the ME in the MOC if the counter reaches the threshold before detecting the predetermined number of instances in which the ME caused a need for an abort.

Microprocessor that performs selective multi-fetch block macro-op cache entry invalidation

A microprocessor includes an instruction cache (IC) of architectural instructions (AIs) and a macro-op cache (MOC) comprising a MOC tag RAM (MTR) and a MOC data RAM (MDR) that holds macro-ops (MOPs) into which AIs have been translated. A MOC entry comprises one MTR entry and one or more MDR entries. A prediction unit (PRU) provides a sequence of fetch block descriptors (FBDs) in program order that describe a corresponding sequence of fetch blocks (FBlks). The PRU comprises a fetch block predictor (FBP) and the MTR which look up a corresponding sequence of fetch block start addresses (FBSAs) to generate respective hit indicators used to generate, for each FBD, a fetch source indicator (FSI) that indicates either the MOC or the IC. An instruction fetch unit (IFU) consumes the sequence of FBDs in program order and initiates a fetch of AIs/MOPs from the IC/MDR based on the FSI.

Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources

A microprocessor includes a macro-op (MOP) cache (MOC) comprising a set-associative MOC tag RAM (MTR) and a MOC data RAM (MDR) managed as a pool of MDR entries. A MOC entry (ME) comprises one MTR entry and one or more MDR entries that hold the MOPs of the ME. The MDR entries of the ME have a program order. Each MDR entry holds MOPs and a next MDR entry pointer. Each MTR entry holds initial MDR entry pointers and specifies the number of the MDR entries of the ME. During ME allocation, the MOC populates the MDR entry pointers to point to the MDR entries based on the program order. In response to an access that hits upon an MTR entry, the MOC fetches the MDR entries according to the program order initially using the initial pointers and subsequently using the next pointers.

Macro-op cache data entry pointers distributed as initial pointers held in tag array and next pointers held in data array for efficient and performant variable length macro-op cache entries

A microprocessor includes execution units that execute macro-operations (MOPs), a decode unit that decodes architectural instructions into MOPs, an instruction fetch unit (IFU) having an instruction cache that caches architectural instructions and a macro-operation cache (MOC) that caches MOPs into which the architectural instructions are decoded. A prediction unit (PRU) predicts a series of fetch blocks (FBs) in a program instruction stream to be fetched by the IFU from the MOC if hit or from the instruction cache otherwise. A branch target buffer (BTB) caches information about previously fetched and decoded FBs. A counter of each BTB entry is incremented when the entry predicts the associated FB is present again. For each FB in the series, the PRU indicates whether the counter has exceeded a threshold for use deciding whether to allocate the MOPs into the MOC in response to an instance of decoding the instructions into the MOPs.

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Folsom, CA, United States of America

Michael N Michael