Micron Technology Incorporated

Round Rock Research, LLC

Apollo Diamond, Inc

Scio Diamond Technology Corporation

Michael Murray

William Henry Radke

Brady L Keays

David A Eggleston

Anthony Moschopoulos

Martin Ragnar Furuhjelm

John S Geldman

Robert C Linares

Patrick Doering

John M Abrahams

Viet Ly

Alicia E Novak

Alfred Genis

William W Dromeshauser

Bryant Linares

John Geldman

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Hybrid memory management

Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.

Programming management data for a memory

Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

Apparatus, methods, and system of NAND defect management

Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.

Flash storage partial page caching

Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.

Split data error correction code circuits

Various embodiments comprise a method, the method comprising determining whether each of a plurality of memory blocks in a memory device is defective, wherein the plurality of memory blocks are organized into memory block groups, and one of the memory block groups comprises a base memory block group; forming a grouping of non-defective memory blocks; forming a remapped grouping of memory blocks that includes a non-defective memory block from the base memory block group and at least one non-defective memory block in another memory block group that includes a defective memory block; and storing a mapping of the remapped grouping in at least one of the memory device and a processor coupled to the memory device.

An electrolytic cell includes a container for holding an electrolyte. A conductively doped single crystal diamond anode electrode is positioned to be disposed within the electrolyte, as is a conductive cathode electrode. Conductors are coupled to the electrodes for coupling to a power supply. An electrolyte inlet and an electrolyte outlet are coupled to the container for causing electrolyte to flow past the electrodes. The anode electrode is downstream from the cathode electrode in one embodiment, such that an electrolyte comprising water is purified by generation of oxygen and/or ozone.

Single crystal diamond electrochemical electrode

A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in 'super blocks' such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Erase block data splitting

Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

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Mountain View, CA, United States of America

Michael Murray