Breakingpoint Systems, Inc.

Agere Systems Inc.

Michael Moriarty

Jonathan Glenn Stroud

Brent Cook

Mark Veteikis

Dennis James Cox

Kristopher Len Raney

Leslie Zsohar

Timothy M Zadigian

Ryan S Clifton

Michael A Roche

A method of processing network traffic within a computing system, comprises at a first configurable logic device (CLD), receiving an ingress network packet from an external network interface, associating the ingress network packet with a timestamp indicating the time of receipt, parsing the ingress network packet to locate a link-layer checksum value and a routing-layer checksum value, determining whether the link-layer and routing-layer checksum values are correct based on the ingress network packet contents, and transmitting the ingress network packet to a second CLD via a high-speed interconnection; and at the second CLD receiving the ingress network packet, parsing the ingress network packet to locate a source address and a destination address, determining a destination and a route for the ingress network packet based at least in part on the source and destination addresses, and transmitting the ingress network packet to the determined destination via the determined route.

High-speed CLD-based pipeline architecture

A method of routing internal network traffic within a computing system comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and routing information, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, and routing the packet according to the routing information.

High-speed CLD-based internal packet routing

A method for enabling virtual data loopback in a computing system may include forwarding a data packet from a first device to a second device; the second device identifying from the data packet egress interface information indicating a first interface for forwarding the data packet out of the computing system; based on the first interface identified from the egress interface information, automatically determining a second interface to the first interface; inserting into the data packet ingress interface information that indicates the second interface; forwarding the data packet, including the ingress interface information, back to the first device; and the first device identifying the ingress interface information indicating the second interface; such that the data packet is looped back to the first device without being communicated via the first or second interface, and such that from the perspective of the first device the data packet was received via the second interface.

Virtual data loopback and/or data capture in a computing system

An automated method for analyzing a plurality of network messages received by a network testing device is disclosed. The method may comprise, during a current window of time, receiving from a target network device a network message associated with an original network message determining a latency value for the received network message comparing the determined latency value with the threshold latency value; and incrementing either the first counter or the second counter based on the comparison of the determined latency value with a threshold latency value. The method may further comprise, at the end of the current window of time, storing the first and second counter values resulting from the analysis of the plurality of original network messages.

Dynamic latency analysis system

A method for managing the capture of packets in a computing system comprises maintaining a buffer tail pointer in a memory of an instruction executing device, receiving a series of packets at an instruction executing device, for each received packet prepending a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer, determining a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer, temporarily writing the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the instruction executing device, and setting the buffer tail pointer to the next free memory location.

Managing the capture of packets in a computing system

A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel.

JTAG-based programming and debug

A method of offloading data intensive tasks from a processor, comprises, at a processor, preparing a TCP packet comprising a TCP header and a data payload, transmitting the TCP packet to a configurable logic device (CLD); and at the CLD, receiving the TCP packet, generating set of TCP segment packets containing, a copy of the TCP header, an incrementing segment sequence identifier, and a portion of the data payload, and transmitting the set of TCP segment packets on an external network interface.

High-speed CLD-based TCP segmentation offload

A network or other type of processor operates to switch packets from an incoming cell stream to an outgoing cell stream. Each received and transmitted cell in a cell stream includes portions of packets, or complete packets or both. Packets are reassembled from incoming cells, and outgoing cells may be created from portions of packets, complete packets or both. The packets in the outgoing cells may be from incoming packets, switched reassembled packets or both. Each incoming and outgoing cell is associated with one virtual channel, and each virtual channel for an outgoing cell may be different from the virtual channel corresponding to the incoming cell or cells from which a packet was reassembled. Switched packets also may have their conversation identifications changed. Partial packets or partial cells that are awaiting completion are retained such that switching capabilities associated with the virtual channel and channel identification modifications may be used.

Processor for packet switching between cell streams with optional virtual channel and channel identification modification

A network processor is enabled to retrieve a packet transmission data structure (PTD) from a memory. The NP parses packet data from the PTD and transmits the data over the network as a network packet. The PTD may include repetition information used by the NP to transmit a plurality of packets. The PTD use transmission interval information to control transmission timing of consecutive network packets. The PTD may include modification information used to modify the data packet portion. The modification may include incrementing, decrementing, or storing a random number into any portion of the data packet. The PTD may include flow control information to determine the next PTD to process. The flow control information may include criteria including acknowledgement criteria and time delay criteria. The packet data portion preferably includes all formatting information applicable to the network.

Growing community of inventors

Austin, TX, United States of America

Michael Moriarty