Intel Corporation

Tahoe Research, Ltd.

Michael Mishaeli

Eliezer Weissmann

Efraim Rotem

Jason W Brandt

Gilbert A Neiger

Zeev Sperber

Alon Naveh

Alexander Gendler

Ganapati Srinivasa

Hisham Shafi

Robert Valentine

Boris Ginzburg

Ron Gabor

James B Crossland

Julius Yuli Mandelblat

Mohan J Kumar

Nadav Shulman

David A Koufaty

Lihu Rappoport

Asit K Mallick

Theodros Yigzaw

Jose Andy Vargas

Scott D Hahn

Baruch Chaikin

Geeyarpuram N Santhanakrishnan

Mark Jay Charney

Paul S Diefenbaugh

Ronny Ronen

Ohad Falik

Ittai Anati

Inder M Sodhi

Dheeraj R Subbareddy

Eugene Gorbatov

Guy M Therien

Shlomo Raikin

Tsvika Kurts

Ehud Cohen

Ashish V Choubal

Ofer Levy

Yoni Aizik

Paolo L Narvaez

Esfir Natanzon

Arik Gihon

Bret L Toll

Rajesh M Sankaran

Baiju V Patel

Doron Rajwan

Barnes Cooper

Andrew J Herdrich

Raghunandan Makaram

H Peter Anvin

Stephen Anthony Fischer

Nir Rosenzweig

Dion Rodgers

Stanislav Shwartsman

Bryant E Bigbee

Anil Aggarwal

Beeman C Strong

Andrew D Henroid

Chris J Newburn

Ido Ouziel

Larisa Novakovsky

Leena K Puthiyedath

Michael W Chynoweth

Rajshree Chabukswar

Rinat Rappoport

Hisham Abu Salah

Yuval Yosef

Avi Mendelson

Benjamin C Chaffin

John L Reid

Gaurav Khanna

Mishali Naik

Itamar S Kazachinsky

Paul Brett

Vivekananthan Sanjeepan

Balaji Vembu

Krishnakanth Venkata Sistla

Eric C Samson

Koichi Yamada

Wei Ey Li

Russell Jerome Fenger

Robert E Gough

Michael N Derr

Konstantin Levit-Gurevich

Adi Yoaz

Zeev Offen

Bryan R White

Jared Warner Stark, Iv

Aamer Jaleel

Douglas Raymond Moran

Ernest Knoll

Rajesh R Shah

Brent D Chartrand

Oded Lempel

Ariel Berkovits

Gustavo P Espinosa

Chen Koren

Tong Li

Ariel Szapiro

Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

Systems, apparatuses, and methods for autonomous functional testing of a processor

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

A processor of an aspect includes a decode unit to decode a user-level suspend thread instruction that is to indicate a first alternate state. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the instruction at a user privilege level. The execution unit in response to the instruction, is to: (a) suspend execution of a user-level thread, from which the instruction is to have been received; (b) transition a logical processor, on which the user-level thread was to have been running, to the indicated first alternate state; and (c) resume the execution of the user-level thread, when the logical processor is in the indicated first alternate state, with a latency that is to be less than half a latency that execution of a thread can be resumed when the logical processor is in a halt processor power state.

Methods, apparatus, and instructions for user-level thread suspension

Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

Apparatuses, methods, and systems for instructions to request a history reset of a processor core

Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

Compacted context state management

Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.

Branch prediction unit in service of short microcode flows

Methods, apparatus, and instructions for user level thread suspension

A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.

System and method for communication using a register management array circuit

In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

System, apparatus and method for probeless field scan of a processor

Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

Error reporting and handling using a common error handler

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

Processor core power event tracing

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Method for booting a heterogeneous system and presenting a symmetric core view

Growing community of inventors

Zichron Yaakov, Israel

Michael Mishaeli