Dalsa Corporation

Michael Miethig

Eric Charles Fox

Charles Russell Smith

Michael George Farrier

Mark Gidney

A circuit includes a programmable delay circuit to provide a sequence of delayed pulses, an A/D circuit to convert a sequence of values into digital values sampled at times defined by the sequence of delayed pulses, and a jitter correction circuit to adjust the programmable delay circuit based on a sequence of digital values from the A/D circuit sampled at times defined by the sequence of delayed pulses.

Automatic A/D convert positioning circuit and method

A fast frame interline transfer charge coupled device imaging sensor includes an imaging section and an storage section. The imaging section includes a plurality of interline transfer registers, each interline transfer register containing a plurality of interline register elements. The imaging section further includes an interline clocking structure, the interline clocking structure including polycrystalline silicon buss lines used as gate electrodes, the polycrystalline silicon buss lines being connected to a metal strapping network, the interline clocking structure causing charge to be transferred between interline register elements of each interline transfer register based on interline clocking signals. The storage section is coupled to the imaging section. The storage section includes a plurality of storage registers, each storage register containing a plurality of storage register elements. The storage section further includes a storage discharge structure and a storage clocking structure. Each storage register element of the storage registers is selectively coupleable through the storage discharge structure to a storage drain. The storage clocking structure has first and second clocking structure parts, the first clocking structure part corresponding to first storage register elements coupled to respective interline registers. The first clocking structure part is coupled to the interline clocking structure so as to cause charge to be transferred from the respective interline registers to the first storage register elements based on the interline clocking signals. The second clocking structure part causes charge to be transferred between storage register elements of each storage register based on frame clocking signals.

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Waterloo, Canada

Michael Miethig