Altera Corporation

Mindspeed Technologies, Inc.

Michael Menghui Zheng

Chong H Lee

Keith Duwel

Divya Vijayaraghavan

Vinson Chan

Lana May Chan

Kalyan Kankipati

Tim Tri Hoang

Ning Xue

Curt Wortman

Allan Thomas Davidson

Neville Carvalho

Binh Ton

Sergey Yuryevich Shumarayev

Bruce B Pedersen

David Wolk Mendel

Weiqi Ding

Kumara Tharmalingam

Tam Minh Nguyen

Andy Turudic

Marwan A Khalaf

Gopi Krishnamurthy

Showi-Min Shen

Seungmyon Park

Daniel Bowersox

Patrick P Chan

An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.

Apparatus for improving power consumption of communication circuitry and associated methods

A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

Transceiver system with reduced latency uncertainty

The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

Scalable interconnect modules with flexible channel bonding

A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.

Digital phase detection circuit and method

Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its 'lock-to-reference' ('LTR') state and its normal &#x201c;lock-to-data&#x201d; (&#x201c;LTD&#x201d;) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device

One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.

Apparatus and methods for activation of an interface on an integrated circuit

Structures and methods to facilitate channel bundling are disclosed. In one embodiment, signal distribution circuitry includes a data path with at least two registers coupled to adjacent sets of data channels in a bundle of data channel sets. In another embodiment, self-switch circuits allow channels in a bundle of channel-sets to switch from bundle-wide signals to locally generated signals after the bundle-wide signals have been synchronously distributed to all channel sets in the bundle. In a particular embodiment, signal distribution circuitry is used to distribute a divided clock signal. In another particular embodiment, signal distribution circuitry is used to distribute enable signals for first-in first-out circuits ('FIFOs') located in channels of each data channel set in a channel set bundle. In a particular aspect of an embodiment, FIFO read and write operations across a channel set bundle are initiated such that a difference between read and write pointer signals is the same in each channel set.

Scalable channel bundling with adaptable channel synchronization

Interface circuitry that is used to interface data between two different clock regimes that may have somewhat different speeds includes the ability to determine which of the clock regimes is faster. Depending on which clock regime is found to be faster, the baseline (nominal difference between data write and data read addresses of a FIFO memory in the interface circuitry) is shifted (i.e., toward the full or empty condition of the FIFO, as is appropriate for which of the clock regimes has been found to be faster). Adjustments may also be made to the threshold(s) used for such purposes as character insertion/deletion and overflow/underflow indication. This technique may allow use of a smaller FIFO and reduce latency of the interface circuitry.

Data interface methods and circuitry with reduced latency

A programmable logic integrated circuit device ('PLD') includes high-speed serial interface ('HSSI') circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).

Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device

An I/O interface for configuring hard IP embedded in a FPGA includes a register load signal, a CSR initialization signal, and a register data signal. After programming the DPRIO registers, the register data controls the operation of the hard IP block. The interface supports both CSR load mode and the MDIO interface. The user-friendly I/O interface eliminates all requirements on the end-user and is virtually transparent to the end-user.

DPRIO for embedded hard IP

Boundary scan cells for driving internal logic and sensing internal logic of integrated circuit use external clocks synchronized with internal functional clocks. Synchronized clocks enable synchronous sampling of internal signals and synchronized of injection signals into a functional portion of the integrated circuit.

Growing community of inventors

Fremont, CA, United States of America

Michael Menghui Zheng