Stratus Technologies Bermuda Ltd.

Stratus Computer Systems, S.a.r.l.

Michael McLoughlin

Gerry Griffin

Jeffrey S Somers

Mark Tetreault

Finbarr Denis Long

John W Doody

Michael James O'Keefe

An apparatus and method for accessing a first local mass storage device or a second local mass storage device in a fault-tolerant server. In one embodiment, the fault-tolerant server establishes communication between a first computing element and a first local mass storage device. The fault-tolerant server also establishes communications between a second computing element and a second local mass storage device. In one embodiment, the first computing element and the second computing element issue substantially similar instruction streams to one of the local mass storage devices.

Apparatus and method for accessing a mass storage device in a fault-tolerant server

An apparatus and method for a first computing element and a second computing element to execute in lockstep in a fault-tolerant server. In one embodiment, the first computing element provides a first instruction to a communications link and the second computing element provides a second instruction to a communications link. In one embodiment, a first local input-output (I/O) subsystem and a second local I/O subsystem are each in communication with the communications link. The first and/or the second local I/O subsystem compare the first instruction and the second instruction. In one embodiment, the first and second local I/O subsystems indicate a fault of the first computing element or the second computing element. Such a fault may be determined by a miscompare of the first instruction and the second instruction.

Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep

Methods and apparatus for implementing high-bandwidth memory subsystems in a multiprocessor computing environment. Each component in the memory subsystem has a recalibration procedure. The computer provides a low-frequency clock signal with a period substantially equal to the duration between recalibration cycles of the components of the memory subsystem. Transitions in the low-frequency clock signal initiate a deterministically-determined delay. Lapse of the delay in turn triggers the recalibration of the components of the memory subsystem, ensuring synchronous recalibration. Synchronizing the recalibration procedures minimizes the unavailability of the memory subsystems, consequently reducing voting errors between CPUs.

Coordinated recalibration of high bandwidth memories in a multiprocessor computer

A method and apparatus for maintaining clock phase alignment among system modules of a fault-tolerant computing system. In one embodiment, a low-frequency system reference clock signal is distributed to all system modules where it is multiplied to generate higher-frequency local clock signals. All local clock signals are then synchronized to the rising edge of the reference clock signal and the first rising edge in relation to a timing event is also identified.

Growing community of inventors

Dublin, Ireland

Michael McLoughlin