Qualcomm Incorporated

Freescale Semiconductor,inc.

Michael McGowan

Iulian Mirea

Douglas Alan Garrity

Dongwon Seo

David R LoCascio

Patrick Drennan

James F McClellan

Todd Robert Sutton

Troy L Stockstad

Brett Christopher Walker

Shahin Mehdizad Taleie

Sang Min Lee

Mukesh Bansal

Derui Kong

Jalal Ahmad Elhusseini

Ganesh Ramachandra Murthy Saripalli

Jenny Kuo

Qadeer Khan

A power amplifier (PA) circuit includes a circuit for generating a supply voltage at an upper voltage rail for a power amplifier (PA). The circuit includes a DC-to-DC converter for generating a voltage from which the supply voltage is generated; a linear amplifier for sourcing or sinking current to or from the upper voltage rail via a capacitor for performing fine adjustment of the supply voltage; a first switching device coupled between an output of the linear amplifier and a lower voltage rail to selectively assist the linear amplifier sink current through the capacitor to deal with actual or anticipated transient response of the supply voltage; and a second switching device coupled between the upper voltage rail and the lower voltage rail to selectively discharge the capacitor in response to actual or anticipated transient response of the supply voltage.

Apparatus and method for assisting envelope tracking with transient response in supply voltage for power amplifier

A current comparator including a first comparator configured to generate a first output signal based on a comparison of a first current to at least a second current; a second comparator configured to generate a second output signal based on a comparison of the first current to at least a third current; and a circuit configured to: direct the first current to the first comparator to perform the comparison of the first current to the at least the second current while blocking the first current from being applied to the second comparator; or direct the first current to the second comparator to perform the comparison of the first current to the at least the third current while blocking the first current from being applied to the first comparator.

Apparatus and method for comparing input current to set of current thresholds

Features and advantages of the present disclosure include a switching regulator and current measurement circuit. In one embodiment, a switching transistor in the switching regulator has a first voltage on a first terminal and a switching voltage on a second terminal. A current measurement circuit has first and second input terminals. A first switch couples the second terminal of the switching transistor to the first terminal of the current measurement circuit when the switching transistor is on, where the second input terminal of the current measurement circuit is coupled to the first terminal of the switching transistor and measurement(s) may be taken. When the switching transistor is off, the first and second input terminals of the current measurement circuit are coupled together, and measurements emulate zero current through the switching transistor.

Current measurments in switching regulators

A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.

Differential mode bandwidth extension technique with common mode compensation

A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current.

Digital calibration of transmit digital to analog converter full scale current

Compensated current cell to scale switching glitches in digital to analog convertors. A compensated current cell is disclosed that includes first and second switching transistors configured to switch an input current between first and second outputs based on first and second input signals, respectively, a first compensation transistor connected to the first input signal to provide a first compensation current that is connected to the second output, and a second compensation transistor connected to the second input signal to provide a second compensation current that is connected to the first output, the first and second compensation transistors having source terminals that are connected together. In another aspect, switching glitches are scaled based on a size difference between the switching transistors and the compensation transistors.

Compensated current cell to scale switching glitches in digital to analog convertors

The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

Method of tiling analog circuits

A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

Method of tiling analog circuits that include resistors and capacitors

A system and apparatus for reducing the effects of circuit mismatch in analog-to-digital converters is disclosed. In one form, an analog-to-digital converter (ADC) includes a switching network operable to couple an analog input received by a sample and hold module to a folding amplifier operable to process the analog input. The ADC further includes an averaging resistive network coupled to the folding amplifier and operable to provide an output representative of a portion of the analog input received by the folding amplifier to produce a digital representation of the analog input.

System and apparatus for reducing the effects of circuit mismatch in analog-to-digital converters

A system and apparatus for reducing offset voltages in folding amplifiers is disclosed. In one form, a folding amplifier for use in an analog-to-digital converter is provided. The folding amplifier includes a first current source operable to be coupled to a first differential pair and a second differential pair. The folding amplifier further includes a switching network coupled between the first current source and the first and second differential pairs and operable to enable coupling the first current source to at least one of the first differential pair and the second differential pair.

Growing community of inventors

Mesa, AZ, United States of America

Michael McGowan