Attollo Engineering, LLC

Flir Systems, Incorporated

Aerius Photonics LLC

Michael MacDougal

Jonathan Charles Geske

Andrew D Hood

John E Bowers

R Jacob Baker

Lloyd Frederick Linder

Chad Shin-deh Wang

Daniel Renner

A PIN photodetector includes an n-type semiconductor layer, an n-type semiconductor cap layer, a first plurality of p-type regions located within the n-type semiconductor cap layer and separated from one another by a distance d, and an absorber layer located between the n-type semiconductor layer and the n-type semiconductor cap layer including the first plurality of p-type regions. The plurality of p-type regions are electrically connected to one another to provide an electrical response to light incident to the PIN photodetector.

PIN photodetector

A hybridized image sensor includes a first die and a second die. The first die includes a first surface, a first plurality of conductive bumps fabricated on the first surface, and a first alignment feature fabricated on the first surface. The second die includes a second surface, a second plurality of conductive bumps fabricated on the second surface, and second alignment features fabricated on the second surface, wherein the first alignment features interact with the second alignment features to align the first plurality of conductive bumps with the second plurality of conductive bumps.

Alignment features for hybridized image sensor

Vertical Cavity Surface Emitting Laser (VCSEL) arrays with vias for electrical connection are disclosed. A Vertical Cavity Surface Emitting Laser (VCSEL) array in accordance with one or more embodiments of the present invention comprises a plurality of first mirrors, a plurality of second mirrors, a plurality of active regions, coupled between the plurality of first mirrors and the plurality of second mirrors, and a heatsink, thermally and mechanically coupled to the second mirror opposite the plurality of active regions, wherein an electrical path to at least one of the plurality of second mirrors is made through a via formed through a depth of the plurality of second mirrors, and a plurality of VCSELs in the VCSEL array are connected in series.

Serially interconnected vertical-cavity surface emitting laser arrays

A single camera capable of capturing high speed laser return pulses for a target, as well as provide imaging information on the background of the target. This capability is enabled by having a read-out integrated circuit (ROIC) capable of extracting both types of information from a pixel of a focal plane array (FPA). Further, an ROIC topology that allows for the ability to distinguish between high frequency and low frequency signal paths, and provide supporting circuitry to process the two paths separately. One path may integrate the low frequency background scene to provide a high fidelity image of the scene. The second path may process high frequency noise and multiple laser pulse returns within a frame. These two paths may be combined to provide a background image with a superimposed laser return.

Dual well read-out integrated circuit (ROIC)

Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.

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Camarillo, CA, United States of America

Michael MacDougal