Xilinx, Inc.

Cyrpess Semiconductor Corp.

Michael Maas

Edward L Grivna

David Erich Tetzlaff

Stephen D Anderson

Khaldoun Bataineh

A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.

Receiver operable to receive data at a lower data rate

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first select signal, a second select signal and a first data stream in response to an input data stream and an exception signal. The second circuit may be configured to generate an output data stream in response to the first data stream, the first select signal and the second select signal. The second circuit may be configured to replace one or more characters of the first data stream.

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Mendota Heights, MN, United States of America

Michael Maas