International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Other

Owl Cyber Defense Solutions, LLC

Michael M Tsao

Bulent Abali

Li Feng Zhang

John Alan Bivens

Parijat Dube

Ronald Mraz

James Anthony Marcella

Steven M Wheeler

Michael K Gschwind

Manoj N Kumar

Makoto Ono

Daniel Michael Kuchta

R Brett Tremaine

Steven Staubly

Doron Shiloach

Three embodiments of one-way cross-domain systems for transferring information from a client in a first security domain to a server in a second separate security domain are disclosed. In addition, three embodiments of bilateral cross-domain systems for transferring first information from a client in a first security domain to a server in a second separate security domain and second information from the server in the second separate security domain to the client in the first security domain are also disclosed. Each of the one-way and bilateral cross-domain systems is based upon a single computer server which employs a number of virtual machines to implement send and receive servers. The single computer server also implements one (for the one-way cross-domain systems) or two (for the bilateral cross-domain systems) virtual one-way data links in either virtual machines or within the hypervisor portion of the operating system.

Single computer-based virtual cross-domain solutions

A method for mirroring data between virtual machines includes intercepting a write command initiated from a virtual machine. Address and data information from the intercepted write command is stored within a queue located within a memory buffer of the primary server. The stored address and data information is transferred, upon filling the queue of the memory buffer of the primary server to a predetermined level, to a dedicated region of the memory of the primary server. The stored address and data information is sent from the dedicated region of the memory of the primary server to a backup server upon filling of the dedicated region of the memory of the primary server to a predetermined level.

Asynchronous data mirroring in memory controller

A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.

Method and apparatus for optimal cache sizing and configuration for large memory systems

A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Translation table and method for compressed data

A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.

Method and apparatus for detection of data errors in tag arrays

We describe, in exemplary embodiments, an on-chip Functional Built-In Self Test ('FBIST') mechanism for testing integrated circuits with internal memory state and complex transaction based interfaces. Such interfaces include system-on-chip applications, memory chip applications, and input/output ('IO') protocol adapter chips.

Apparatus and method for integrated functional built-in self test for an ASIC

A method for sending and receiving asynchronous signals using optical techniques. The present invention implements open-drain circuit signaling utilizing a Finite State Machine and additional logic to reduce power requirements when transmitting asynchronous information via an optical transmission line. An embodiment exploits the 8 bit/10 bit encoder to detect errors and signal the beginning of valid data along the transmission line. The asynchronous signals may be transmitted during transitions in the Finite State Machine.

Exchanging asynchronous system information using optical transmission

A single instruction multiple data stream ('SIMD') processor includes multiple processing elements ('PEs'). Each PE includes a memory, a first multiplexer, an instruction register, a local instruction buffer for storing an instruction and a unit for modifying the instruction, in its entirety, to create a modified instruction. The modified instruction is stored in the local instruction buffer until it is executed. This structure modifies the instruction broadcast from the central controller of an SIMD computer in its entirety and creates modified instructions which can be unique to each PE.

System with flexible local control for modifying same instruction

This invention is a high performance, standard IO interconnect 'bridge' hardware for a parallel machine with a packet switching network in place. Combining new hardware and new software, this bridge connects parallel processors to the external world. The hardware is a 'bridge' connecting an internal inter-processor switch to external asynchronous transfer node networks. The software is a 'mirror' for making the connections. The invention provides high bandwidth, low latency and deterministic performance, and is inexpensive to build.

Growing community of inventors

Yorktown Heights, NY, United States of America

Michael M Tsao