Xilinx, Inc.

Michael M Matera

Robert W Wells

Robert D Patrie

Eric Thorne

Glenn O'Rourke

Jongheon Jeong

Jae Cho

Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

Method and apparatus for self-regulated burn-in of an integrated circuit

Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

Providing fault coverage of interconnect in an FPGA

Described are a system and method for quickly and accurately testing sequential storage elements on programmable logic devices for zero-hold-time compliance. A programmable logic device is configured such that both the data and clock terminals of a selected sequential logic element connect to an input pin of the programmable logic device and the output terminal of the sequential logic element connects to an output pin of the programmable logic device. A circuit tester connected to the input pin then generates a signal transition on the input pin so that the signal transition traverses both the data and clock paths in a race to the sequential storage element. The circuit tester also includes an input terminal that monitors the PLD output pin to determine whether the storage element contains the correct data after the storage element is clocked. Incorrect data stored in the sequential storage element after the storage element is clocked indicates that the clock signal arrived before the data, and therefore that the selected storage element violated the zero-hold-time requirement in the specified configuration.

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Santa Cruz, CA, United States of America

Michael M Matera