Intel Corporation

Michael M DeSmith

David Gregory Figueroa

Yuan-Liang Li

Dong Zhong

Jennifer A Hester

David Stewart Dunning

Jung S Kang

Richard S Jensen

Srikrishnan Venkataraman

Yi-Feng Liu

Jayashree Kar

Sudarshan D Solanki

Peter Peide Jeng

Md Monzur Hossain

Priyavadan Ramdas Patel

Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time 'T' of the lanes is determined. The number of lanes 'N' in the I/O interface is identified. The programmed lane to lane delay &#x201c;D&#x201d; is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.

Method to control delay between lanes

A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and the underlying epitaxial silicon layer. A larger interface area between N-doped and P-doped regions generally increases the capacitance. By providing the N-doped strip portions, as opposed to a continuous N-doped region, the combined interface area between the N-doped strip portions and the underlying epitaxial silicon layer is reduced. However, more interface area is provided between the N-doped strip portions and the P-doped strip portions. A circuit simulation indicates that junction capacitance per unit peripheral length is 0.41 fF/&#x3bc;m, while the junction capacitance per unit area is 0.19 fF/&#x3bc;m^2. Junction capacitance per unit peripheral length thus scales faster than junction capacitance per unit area.

Intrinsic decoupling capacitor

According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.

System to control effective series resistance of decoupling capacitor

According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Capacitor-related systems for addressing package/motherboard resonance

According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

A switch circuit having low charge dumping characteristics includes multiple parallel connected switching transistors and one or more associated cancellation transistors. The switching transistors perform basic switching functions within the switch circuit in response to a digital signal. During transitions of the digital signal, the switching transistors dump charge on an output node thereof due to parasitic capacitances within the devices. The cancellation transistor(s) dumps charge of an opposite polarity on the output node to cancel the charge dumped by the switching transistors. Two switching transistors are used for each cancellation transistor so that equal sized devices can be used throughout the switch circuit.

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Beaverton, OR, United States of America

Michael M DeSmith