Xilinx, Inc.

Michael Leonard Simmons

Tuyet Ngoc Simmons

Andrew John Flynn

Noel John Manicle

Christopher Lanseng Ling

Conrad A Theron

Andrew W Lai

Mihai G Statovici

Brian Sadler

Walter H Edmondson

A network appliance, and a system and user interface therefor, are described. The network appliance includes a file capture module is to obtain files transmitted via a network and to load data from the files into a database. A user interface for communicating with the server includes a first set of fields and a second set of fields. The first set of fields are for selecting data from the database and the second set of fields are for selecting indices for charting the data selected with the first set of fields. A data processing module is configured to retrieve data from the database responsive to the data selected with the first set of fields, to chart the data retrieved responsive to the indices selected with the second set of fields, and to output a graph of the data charted to a server having access to the database.

Network appliance for data collection and processing from multiple locations and data schema therefor

A test setup is provided to test differential signals outputs from the I/O block (IOB) pairs in an integrated circuit (IC). The test setup allows elimination of the external 100 Ohm resistors provided across the differential outputs on a device under test (DUT) test board containing the IC by taking advantage of a 100 Ohm resistor built into the IC between a portion of the IOB pairs. An IOB pair being tested may have its differential output terminal pair shorted to the differential output terminal pair of the IOBs having the internal 100 Ohm resistor.

Testing differential signal standards using device under test's built in resistors

Method and apparatus for providing shorted pin information for constructing a device under test (DUT) board for integrated circuit testing is described. In one example, an interface to an application module that implements pin-shorting rules associated generally with a plurality of integrated circuits and stores package files associated with specific ones of the integrated circuits is provided. A device and a package defining one of the plurality of integrated circuits are selected via the interface. At least one query is executed against the pin-shorting rules and the package files stored in the database via the interface. A shorted pin plan for the device and the package as selected is generated based on information obtained in response to the at least one query.

Method and apparatus for providing shorted pin information for integrated circuit testing

A server system for receiving and processing manufacturing data from a plurality of semi-conductor manufacturers is disclosed. The server system includes: a file capture module for receiving the manufacturing data from the plurality of semi-conductor manufacturers; a format conversion module coupled to the file capture module, the format conversion module converting the manufacturing data to a standard database format for storage in a database; a query builder module coupled to a client web browser for interactively changing contents of the client web browser depending upon a plurality of client selections on the client web browser, the query builder module configured to build a final query based on the plurality of client selections; and a report generation module coupled to the database and the query builder module, the report generation module generating a report based on the final query.

Method and system for collection, analysis, and display of semiconductor manufacturing information

Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

Growing community of inventors

Monte Sereno, CA, United States of America

Michael Leonard Simmons