International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Michael Leo Scollard

Challis Llewellyn Purrington

Gary Roy Shippy

Dhruv Manmohandas Desai

Christopher Landon Wood

Nickolas John Gruendler

Henry Gaines McMillan

Malcolm Scott Ware

Michael Joseph Steinmetz

Carl A Morrell

James Edward Hughes

Ivan R Zapata

Robert Joseph Evans

Kamran Amini

Victor A Stankevich

William Gavin Holland

Alfredo Aldereguia

Scott Neil Dunham

Randolph Scot Kolvick

Christopher Collier West

Heidi D Williams

Sumanta Kumar Bahali

Tu T Dang

Michael Charles Elles

Paul Anthony Smith

Joseph Curtis Diepenbrock

Juan Q Hernandez

Robert M Piper

Brian E Bigelow

Robert L Ayers

Paul Maylon Smith

Troy S Voytko

Richard P Southers

Maya P Yarbrough

Dwayne A Lowe

Christopher C Moody

Terry L Sawyers

Paul Douglas Bashor

A robust printed circuit board (PCB) that includes at least two power layers that are used in providing power to components connected to the PCB. The power layers may be a power plane layer and a ground plane layer. The power plane layer is situated such that its edge is pulled back a second distance from the planar edge of the PCB. The ground plane layer is situated such that its edge is pulled back a first distance from the planar edge of the PCB. The second distance and the first distance are different, and as a result, the planar edges of the power plane layer and the ground plane layer respectively do not coincide.

Robust power plane configuration in printed circuit boards

One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Use of hashing function to distinguish random and repeat errors in a memory system

Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.

Preemptive thermal management for a computing system based on cache performance

The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.

Detecting faulty CPU heat sink coupling during system power-up

A method and system and calibration technique for power measurement and management over multiple time frames provides responsive power control while meeting global system power consumption and power dissipation limits. Power output of one or more system power supplies is measured and processed to produce power values over multiple differing time frames. The measurements from the differing time frames are used to determine whether or not system power consumption should be adjusted and then one or more devices is power-managed in response to the determination. The determination may compare a set of maximum and/or minimum thresholds to each of the measurements from the differing time frames. A calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor calibration is made at the common mode voltage of the power supply output.

Method, system and calibration technique for power measurement and management over multiple time frames

Power is allocated to blades based on an estimate of the actual power they are expected to use rather than their maximum-power draw-value. To protect against situations where the estimated actual-power draw-value is exceeded, a hardware comparator monitors the blade system load against a predetermined threshold value set by a management module (MM) based on user input. If this threshold value is exceeded, a throttle latch is triggered, based on a signal from a service processor monitoring the blade system load. The output of this latch directly engages throttling. The service processor also monitors the output of the latch and communicates information regarding the throttling to the MM for evaluation.

Throttle management for blade system

A calibration technique provides for precision calibration of system power measurement. The calibration technique uses a precision reference resistor and voltage reference controlled current source to introduce a voltage drop from the input side of a power supply sense resistor. Calibration measurements are thereby made for voltages substantially equal to the voltage of the power supply output, so that differential measurements are made at substantially the same common-mode voltage by appropriate selection of the relationship of the resistance of the precision reference resistor and the resistance of the sense resistor, where the common-mode voltage of the measurement is substantially equal to the power supply output voltage.

Calibration technique for power measurement and management over multiple time frames

A method and system are disclosed to enable and control power reduction in a blade/chassis system. A 'maximum power reduction' attribute is stored in the VPD of the blade (or can otherwise be input to or retrieved or calculated by the management entity). The management module of the chassis in which the blades and power supplies are located uses this information to manage the power reduction of blades when the system is operating in an over-subscription mode and a power supply fails. If throttling is required, the system knows the amount of power reduction available for each blade and controls the throttling by spreading it out among the blades in the system so that, ideally, no blade will cease operation altogether.

Programmable throttling in blade/chassis power management

Detecting, predicting, and diagnosing faults in a cooling system. According to one embodiment, a heat sink is in thermal contact with a heat-generating electronic component. When a temperature differential between the electronic component and the heat sink exceeds a set point, a fault signal is generated. The set point may be empirically or theoretically determined. The set point may be a static set point, or it may be a dynamic set point determined according to real-time operational parameters of the system. The system may be implemented with predictive failure analysis (PFA) to provide a more reliable, efficient, inexpensive, and robust computer system.

Method and apparatus for detecting heat sink faults

A signal channel extends from motherboard to a daughter card across an edge connection. The daughter card includes a conductive plane that is held at a constant electrical potential. In order to compensate for a number of sources of inductance within the signal line at the edge connection, a circuit trace forming a portion of the signal channel includes an enlarged portion, spaced inward along the daughter card from the contact pads forming the edge connection, that adds capacitive coupling of the signal channel with the conductive plane.

Signal channel configuration providing increased capacitance at a card edge connection

A method of controlling the power-on of a computer system by providing a plurality of monitor lines interconnected with respective components of the computer system, monitoring the lines using a control circuit in response to a power-on reset signal, and executing a system power-on sequence in response to a determination by the control circuit that the components of the computer system are functioning properly. If the computer system has a plurality of CPU slots, the control circuit determines if a CPUs or terminator cartridges is plugged into the CPU slots, and determines that a properly matched CPU has been installed into the system, and that multiple CPUs contain compatible power supply requirements. Finally, the control circuit can determine that a power regulator is functioning properly.

Method and system for controlling a power on sequence in response to monitoring respective components of a computer system with multiple CPU sockets to determine proper functionality

Growing community of inventors

Raleigh, NC, United States of America

Michael Leo Scollard